| 2010 |
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| 10 | Generalized pipelined tomlinson-harashima precoder design methodology with build-in arbitrary speed-up factors. Yen-Liang Chen, An-Yeu Wu. IEEE Transactions on Signal Processing (58): 2375-2382 (2010). Web SearchBibTeXDownload |
| 9 | A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm. Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu. IEEE Trans. on Circuits and Systems (57-II): 430-434 (2010). Web SearchBibTeXDownload |
| 2008 |
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| 8 | An efficient methodology to evaluate nanoscale circuit fault-tolerance performance based on belief propagation. Huifei Rao, Jie Chen, V. H. Zhao, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu. ISCAS 2008, 608-611. Web SearchBibTeXDownload |
| 7 | Cost-effective echo and NEXT canceller designs for 10GBASE-T ethernet system. Yen-Liang Chen, Cheng-Zhou Zhan, An-Yeu Wu. ISCAS 2008, 3150-3153. Web SearchBibTeXDownload |
| 6 | Cost-Effective Joint Echo-NEXT Canceller Designs for 10GBase-T Ethernet Systems Based on a Shortened Impulse Response Filter (SIRF) Scheme. Yen-Liang Chen, Ming-Feng Hsu, Jyh-Ting Lai, An-Yeu Wu. Signal Processing Systems (52): 59-73 (2008). Web SearchBibTeXDownload |
| 2007 |
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| 5 | Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design. Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao. ISCAS 2007, 1803-1806. Web SearchBibTeXDownload |
| 2006 |
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| 4 | A portable all-digital pulsewidth control loop for SOC applications. Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu. ISCAS 2006. Web SearchBibTeXDownload |
| 3 | A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu. ISCAS 2006. Web SearchBibTeXDownload |
| 2 | A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System. Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, An-Yeu Wu. SiPS 2006, 309-312. Web SearchBibTeXDownload |
| 2005 |
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| 1 | A scalable DCO design for portable ADPLL designs. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu. ISCAS (6) 2005, 5449-5452. Web SearchBibTeXDownload |
