| 2012 |
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| 17 | ORION 2.0: A Power-Area Simulator for Interconnection Networks. Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi. IEEE Trans. VLSI Syst. (20): 191-196 (2012). Web SearchBibTeXDownload |
| 2009 |
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| 16 | ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration. Andrew B. Kahng, Bin Li, Li-Shiuan Peh, Kambiz Samadi. DATE 2009, 423-428. Web SearchBibTeXDownload |
| 2007 |
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| 15 | Analytical thermal placement for VLSI lifetime improvement and minimum performance variation. Andrew B. Kahng, Sung-Mo Kang, Wei Li, Bao Liu. ICCD 2007, 71-77. Web SearchBibTeXDownload |
| 2005 |
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| 14 | Performance Driven OPC for Mask Cost Reduction. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang. ISQED 2005, 270-275. Web SearchBibTeXDownload |
| 2004 |
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| 13 | Quantum-Dot Cellular Automata (QCA) circuit partitioning: problem modeling and solutions. Dominic A. Antonelli, Danny Z. Chen, Timothy J. Dysart, Xiaobo Sharon Hu, Andrew B. Kahng, Peter M. Kogge, Richard C. Murphy, Michael T. Niemier. DAC 2004, 363-368. Web SearchBibTeXDownload |
| 12 | Toward a methodology for manufacturability-driven design rule exploration. Luigi Capodieci, Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang. DAC 2004, 311-316. Web SearchBibTeXDownload |
| 2003 |
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| 11 | A cost-driven lithographic correction methodology based on off-the-shelf sizing tools. Puneet Gupta, Andrew B. Kahng, Dennis Sylvester, Jie Yang. DAC 2003, 16-21. Web SearchBibTeXDownload |
| 10 | Improved a priori interconnect predictions and technology extrapolation in the GTX system. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester. IEEE Trans. VLSI Syst. (11): 3-14 (2003). Web SearchBibTeXDownload |
| 2002 |
|---|
| 9 | Provably good global buffering by generalized multiterminalmulticommodity flow approximation. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky. IEEE Trans. on CAD of Integrated Circuits and Systems (21): 263-274 (2002). Web SearchBibTeXDownload |
| 2001 |
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| 8 | Provably good global buffering by multi-terminal multicommodity flow approximation. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky. ASP-DAC 2001, 120-125. Web SearchBibTeXDownload |
| 7 | Practical Approximation Algorithms for Separable Packing Linear Programs. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky. WADS 2001, 325-337. Web SearchBibTeXDownload |
| 2000 |
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| 6 | GTX: the MARCO GSRC technology extrapolation system. Andrew E. Caldwell, Yu Cao, Andrew B. Kahng, Farinaz Koushanfar, Hua Lu, Igor L. Markov, Michael Oliver, Dirk Stroobandt, Dennis Sylvester. DAC 2000, 693-698. Web SearchBibTeXDownload |
| 5 | METRICS: a system architecture for design process optimization. Stephen Fenstermaker, David George, Andrew B. Kahng, Stefanus Mantik, Bart Thielges. DAC 2000, 705-710. Web SearchBibTeXDownload |
| 4 | Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design. Yu Cao, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester. ICCAD 2000, 56-61. Web SearchBibTeX |
| 3 | Provably Good Global Buffering Using an Available Buffer Block Plan. Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky. ICCAD 2000, 104-109. Web SearchBibTeX |
| 1998 |
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| 2 | Guest Editorial. Darrell Conklin, Tadeusz A. Wysocki, Hamid Sharif, L. C. Gundersen, P. P. Leahy, W. Hill, Jyh-Horng Wen, Shiuh-Jeng Wang, Yuh-Ren Tsai, Keh-Ming Lu. IEEE Trans. on CAD of Integrated Circuits and Systems (17): 1-2 (1998). Cited by 2Web SearchBibTeXDownload |
| 1995 |
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| 1 | Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger. IEEE Trans. on CAD of Integrated Circuits and Systems (14): 890-896 (1995). Web SearchBibTeXDownload |
