Asha Balijepalli
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| 2010 |
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| 7 | Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao. IEEE Trans. VLSI Syst. (18): 666-670 (2010). Web SearchBibTeXDownload |
| 2009 |
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| 6 | The Predictive Technology Model in the Late Silicon Era and Beyond. Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao. Foundations and Trends in Electronic Design Automation (3): 305-401 (2009). Web SearchBibTeXDownload |
| 5 | Compact modeling of a PD SOI MESFET for wide temperature designs. Asha Balijepalli, Joseph Ervin, W. Lepkowski, Yu Cao, T. J. Thornton. Microelectronics Journal (40): 1264-1273 (2009). Web SearchBibTeXDownload |
| 2008 |
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| 4 | A Simplified Model of Carbon Nanotube Transistor with Applications to Analog and Digital Design. Saurabh Sinha, Asha Balijepalli, Yu Cao. ISQED 2008, 502-507. Web SearchBibTeXDownload |
| 2007 |
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| 3 | Modeling and Analysis of Non-Rectangular Gate for Post-Lithography Circuit Simulation. Ritu Singhal, Asha Balijepalli, Anupama Subramaniam, Frank Liu, Sani R. Nassif, Yu Cao. DAC 2007, 823-828. Web SearchBibTeXDownload |
| 2 | Compact modeling of carbon nanotube transistor for early stage process-design exploration. Asha Balijepalli, Saurabh Sinha, Yu Cao. ISLPED 2007, 2-7. Web SearchBibTeXDownload |
| 1 | Compact Modeling of a PD SOI MESFET for Wide Temperature Designs. Asha Balijepalli, Joseph Ervin, Yu Cao, Trevor Thornton. ISQED 2007, 133-138. Web SearchBibTeXDownload |
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