| 2011 |
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| 13 | ACCESS: Smart scheduling for asymmetric cache CMPs. Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das. HPCA 2011, 527-538. Web SearchBibTeXDownload |
| 12 | Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. ISCA 2011, 69-80. Web SearchBibTeXDownload |
| 11 | A case for heterogeneous on-chip interconnects for CMPs. Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das. ISCA 2011, 389-400. Web SearchBibTeXDownload |
| 10 | RAFT: A router architecture with frequency tuning for on-chip networks. Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das. J. Parallel Distrib. Comput. (71): 625-640 (2011). Web SearchBibTeXDownload |
| 9 | METE: meeting end-to-end QoS in multicores through system-wide resource management. Akbar Sharifi, Shekhar Srikantaiah, Asit K. Mishra, Mahmut T. Kandemir, Chita R. Das. SIGMETRICS 2011, 13-24. Web SearchBibTeXDownload |
| 2010 |
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| 8 | CPM in CMPs: Coordinated Power Management in Chip-Multiprocessors. Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das. SC 2010, 1-12. Web SearchBibTeXDownload |
| 7 | Coordinated power management of voltage islands in CMPs. Asit K. Mishra, Shekhar Srikantaiah, Mahmut T. Kandemir, Chita R. Das. SIGMETRICS 2010, 359-360. Web SearchBibTeXDownload |
| 6 | Towards characterizing cloud backend workloads: insights from Google compute clusters. Asit K. Mishra, Joseph L. Hellerstein, Walfredo Cirne, Chita R. Das. SIGMETRICS Performance Evaluation Review (37): 34-41 (2010). Web SearchBibTeXDownload |
| 2009 |
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| 5 | Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das. HPCA 2009, 175-186. Web SearchBibTeXDownload |
| 4 | A case for dynamic frequency tuning in on-chip networks. Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar Iyer, Narayanan Vijaykrishnan, Chita R. Das. MICRO 2009, 292-303. Web SearchBibTeXDownload |
| 3 | A case for integrated processor-cache partitioning in chip multiprocessors. Shekhar Srikantaiah, Reetuparna Das, Asit K. Mishra, Chita R. Das, Mahmut T. Kandemir. SC 2009. Web SearchBibTeXDownload |
| 2008 |
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| 2 | Performance and power optimization through data compression in Network-on-Chip architectures. Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar Iyer, Mazin S. Yousif, Chita R. Das. HPCA 2008, 215-225. Web SearchBibTeXDownload |
| 1 | MIRA: A Multi-layered On-Chip Interconnect Router Architecture. Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. ISCA 2008, 251-261. Web SearchBibTeXDownload |
