Changkyu Kim

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2011
27Moguls: a model to explore the memory hierarchy for bandwidth improvements. Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen. ISCA 2011, 377-388. Web SearchBibTeXDownload
26Fast Updates on Read-Optimized Databases Using Multi-Core CPUs. Jens Krüger, Changkyu Kim, Martin Grund, Nadathur Satish, David Schwalb, Jatin Chhugani, Hasso Plattner, Pradeep Dubey, Alexander Zeier. PVLDB (5): 61-72 (2011). Web SearchBibTeXDownload
25PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors. Jason Sewall, Jatin Chhugani, Changkyu Kim, Nadathur Satish, Pradeep Dubey. PVLDB (4): 795-806 (2011). Web SearchBibTeXDownload
2010
24Performance and Energy Implications of Many-Core Caches for Throughput Computing. Christopher J. Hughes, Changkyu Kim, Yen-Kuang Chen. IEEE Micro (30): 25-35 (2010). Web SearchBibTeXDownload
23Debunking the 100X GPU vs. CPU myth: an evaluation of throughput computing on CPU and GPU. Victor W. Lee, Changkyu Kim, Jatin Chhugani, Michael Deisher, Daehyun Kim, Anthony D. Nguyen, Nadathur Satish, Mikhail Smelyanskiy, Srinivas Chennupaty, Per Hammarlund, Ronak Singhal, Pradeep Dubey. ISCA 2010, 451-460. Web SearchBibTeXDownload
223.5-D Blocking Optimization for Stencil Computations on Modern CPUs and GPUs. Anthony D. Nguyen, Nadathur Satish, Jatin Chhugani, Changkyu Kim, Pradeep Dubey. SC 2010, 1-13. Web SearchBibTeXDownload
21FAST: fast architecture sensitive tree search on modern CPUs and GPUs. Changkyu Kim, Jatin Chhugani, Nadathur Satish, Eric Sedlar, Anthony D. Nguyen, Tim Kaldewey, Victor W. Lee, Scott A. Brandt, Pradeep Dubey. SIGMOD Conference 2010, 339-350. Web SearchBibTeXDownload
20Fast sort on CPUs and GPUs: a case for bandwidth oblivious SIMD sort. Nadathur Satish, Changkyu Kim, Jatin Chhugani, Anthony D. Nguyen, Victor W. Lee, Daehyun Kim, Pradeep Dubey. SIGMOD Conference 2010, 351-362. Web SearchBibTeXDownload
2009
19Efficient shared cache management through sharing-aware replacement and streaming-aware insertion policy. Yu Chen, Wenlong Li, Changkyu Kim, Zhizhong Tang. IPDPS 2009, 1-11. Web SearchBibTeXDownload
18Interactive Modeling, Simulation and Control of Large-Scale Crowds and Traffic. Ming C. Lin, Stephen J. Guy, Rahul Narain, Jason Sewall, Sachin Patil, Jatin Chhugani, Abhinav Golas, Jur P. van den Berg, Sean Curtis, David Wilkie, Paul Merrell, Changkyu Kim, Nadathur Satish, Pradeep Dubey, Dinesh Manocha. MIG 2009, 94-103. Web SearchBibTeXDownload
17Sort vs. Hash Revisited: Fast Join Implementation on Modern Multi-Core CPUs. Changkyu Kim, Eric Sedlar, Jatin Chhugani, Tim Kaldewey, Anthony D. Nguyen, Andrea Di Blas, Victor W. Lee, Nadathur Satish, Pradeep Dubey. PVLDB (2): 1378-1389 (2009). Web SearchBibTeXDownload
16ClearPath: highly parallel collision avoidance for multi-agent simulation. Stephen J. Guy, Jatin Chhugani, Changkyu Kim, Nadathur Satish, Ming C. Lin, Dinesh Manocha, Pradeep Dubey. Symposium on Computer Animation 2009, 177-187. Web SearchBibTeXDownload
2008
15Second Life and the New Generation of Virtual Worlds. Sanjeev Kumar, Jatin Chhugani, Changkyu Kim, Daehyun Kim, Anthony D. Nguyen, Pradeep Dubey, Christian Bienia, Youngmin Kim. IEEE Computer (41): 46-53 (2008). Web SearchBibTeXDownload
14Atomic Vector Operations on Chip Multiprocessors. Sanjeev Kumar, Daehyun Kim, Mikhail Smelyanskiy, Yen-Kuang Chen, Jatin Chhugani, Christopher J. Hughes, Changkyu Kim, Victor W. Lee, Anthony D. Nguyen. ISCA 2008, 441-452. Web SearchBibTeXDownload
13Multitasking workload scheduling on flexible-core chip multiprocessors. Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger. PACT 2008, 187-196. Web SearchBibTeXDownload
12Multitasking workload scheduling on flexible core chip multiprocessors. Divya Gulati, Changkyu Kim, Simha Sethumadhavan, Stephen W. Keckler, Doug Burger. SIGARCH Computer Architecture News (36): 46-55 (2008). Web SearchBibTeXDownload
2007
11On-Chip Interconnection Networks of the TRIPS Chip. Paul Gratz, Changkyu Kim, Karthikeyan Sankaralingam, Heather Hanson, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger. IEEE Micro (27): 41-50 (2007). Web SearchBibTeXDownload
10A NUCA Substrate for Flexible CMP Cache Sharing. Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler. IEEE Trans. Parallel Distrib. Syst. (18): 1028-1040 (2007). Web SearchBibTeXDownload
9Composable Lightweight Processors. Changkyu Kim, Simha Sethumadhavan, M. S. Govindan, Nitya Ranganathan, Divya Gulati, Doug Burger, Stephen W. Keckler. MICRO 2007, 381-394. Web SearchBibTeXDownload
2006
8Implementation and Evaluation of On-Chip Network Architectures. Paul Gratz, Changkyu Kim, Robert G. McDonald, Stephen W. Keckler, Doug Burger. ICCD 2006. Web SearchBibTeXDownload
7Distributed Microarchitectural Protocols in the TRIPS Prototype Processor. Karthikeyan Sankaralingam, Ramadass Nagarajan, Robert G. McDonald, Rajagopalan Desikan, Saurabh Drolia, M. S. Govindan, Paul Gratz, Divya Gulati, Heather Hanson, Changkyu Kim, Haiming Liu, Nitya Ranganathan, Simha Sethumadhavan, Sadia Sharif, Premkishore Shivakumar, Stephen W. Keckler, Doug Burger. MICRO 2006, 480-491. Web SearchBibTeXDownload
2005
6A NUCA substrate for flexible CMP cache sharing. Jaehyuk Huh, Changkyu Kim, Hazim Shafi, Lixin Zhang, Doug Burger, Stephen W. Keckler. ICS 2005, 31-40. Web SearchBibTeXDownload
2004
5TRIPS: A polymorphous architecture for exploiting ILP, TLP, and DLP. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Nitya Ranganathan, Doug Burger, Stephen W. Keckler, Robert G. McDonald, Charles R. Moore. TACO (1): 62-93 (2004). Web SearchBibTeXDownload
2003
4Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches. Changkyu Kim, Doug Burger, Stephen W. Keckler. IEEE Micro (23): 99-107 (2003). Web SearchBibTeXDownload
3Exploiting ILP, TLP, and DLP with the Polymorphous TRIPS Architecture. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore. IEEE Micro (23): 46-51 (2003). Web SearchBibTeXDownload
2Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore. ISCA 2003, 422-433. Web SearchBibTeXDownload
2002
1An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches. Changkyu Kim, Doug Burger, Stephen W. Keckler. ASPLOS 2002, 211-222. Web SearchBibTeXDownload
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