| 2012 |
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| 8 | Leakage reduction through optimization of regular layout parameters. Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao. Microelectronics Journal (43): 25-33 (2012). Web SearchBibTeXDownload |
| 2010 |
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| 7 | Simulation of random telegraph Noise with 2-stage equivalent circuit. Yun Ye, Chi-Chao Wang, Yu Cao. ICCAD 2010, 709-713. Web SearchBibTeXDownload |
| 6 | Modeling and Analysis of the Nonrectangular Gate Effect for Postlithography Circuit Simulation. Ritu Singhal, Asha Balijepalli, Anupama R. Subramaniam, Chi-Chao Wang, Frank Liu, Sani R. Nassif, Yu Cao. IEEE Trans. VLSI Syst. (18): 666-670 (2010). Web SearchBibTeXDownload |
| 5 | Workload-adaptive process tuning strategy for power-efficient multi-core processors. Jungseob Lee, Chi-Chao Wang, Hamid Ghasemil, Lloyd Bircher, Yu Cao, Nam Sung Kim. ISLPED 2010, 225-230. Web SearchBibTeXDownload |
| 2009 |
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| 4 | Pathfinding for 22nm CMOS designs using Predictive Technology Models. Xia Li, Wei Zhao, Yu Cao, Zhi Zhu, Jooyoung Song, David Bang, Chi-Chao Wang, Seung H. Kang, Joseph Wang, Matt Nowak, Nick Yu. CICC 2009, 227-230. Web SearchBibTeXDownload |
| 3 | The Predictive Technology Model in the Late Silicon Era and Beyond. Yu Cao, Asha Balijepalli, Saurabh Sinha, Chi-Chao Wang, Wenping Wang, Wei Zhao. Foundations and Trends in Electronic Design Automation (3): 305-401 (2009). Web SearchBibTeXDownload |
| 2 | Modeling of layout-dependent stress effect in CMOS design. Chi-Chao Wang, Wei Zhao, Frank Liu, Min Chen, Yu Cao. ICCAD 2009, 513-520. Web SearchBibTeXDownload |
| 2008 |
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| 1 | Design rule optimization of regular layout for leakage reduction in nanoscale design. Anupama R. Subramaniam, Ritu Singhal, Chi-Chao Wang, Yu Cao. ASP-DAC 2008, 474-479. Web SearchBibTeXDownload |
