Chia-Tsun Wu
Loading Google Thumbnails...
from Google Images |
- Sorted by Year/Conf, Year/Citation, Citation
| 2010 | ||
|---|---|---|
| 4 | A Two-Cycle Lock-In Time ADPLL Design Based on a Frequency Estimation Algorithm. Chia-Tsun Wu, Wen-Chung Shen, Wei Wang, An-Yeu Wu. IEEE Trans. on Circuits and Systems (57-II): 430-434 (2010). Web SearchBibTeXDownload | |
| 2006 | ||
| 3 | A frequency estimation algorithm for ADPLL designs with two-cycle lock-in time. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu. ISCAS 2006. Web SearchBibTeXDownload | |
| 2 | A portable all-digital pulsewidth control loop for SOC applications. Wei Wang, I-Chyn Wey, Chia-Tsun Wu, An-Yeu Wu. ISCAS 2006. Web SearchBibTeXDownload | |
| 2005 | ||
| 1 | A scalable DCO design for portable ADPLL designs. Chia-Tsun Wu, Wei Wang, I-Chyn Wey, An-Yeu Wu. ISCAS (6) 2005, 5449-5452. Web SearchBibTeXDownload | |
from DBLP and Google Scholar