Dajiang Zhou
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| 2011 |
|---|
| 8 | Cache Based Motion Compensation Architecture for Quad-HD H.264/AVC Video Decoder. Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto. IEICE Transactions (94-C): 439-447 (2011). Web SearchBibTeXDownload |
| 7 | A 98 GMACs/W 32-Core Vector Processor in 65 nm CMOS. Xun He, Xin Jin, Minghui Wang, Dajiang Zhou, Satoshi Goto. IEICE Transactions (94-A): 2609-2618 (2011). Web SearchBibTeXDownload |
| 6 | A 530 Mpixels/s Intra Prediction Architecture for Ultra High Definition H.264/AVC Encoder. Gang He, Dajiang Zhou, Jinjia Zhou, Tianruo Zhang, Satoshi Goto. IEICE Transactions (94-C): 419-427 (2011). Web SearchBibTeXDownload |
| 5 | A 98 GMACs/W 32-core vector processor in 65nm CMOS. Xun He, Dajiang Zhou, Xin Jin, Satoshi Goto. ISLPED 2011, 373-378. Web SearchBibTeXDownload |
| 4 | A high parallel macro block level layered LDPC decoding architecture based on dedicated matrix reordering. Qian Xie, Qian He, Xiao Peng, Ying Cui, Zhixiang Chen, Dajiang Zhou, Satoshi Goto. SiPS 2011, 122-127. Web SearchBibTeXDownload |
| 3 | Ultra low power QC-LDPC decoder with high parallelism. Ying Cui, Xiao Peng, Zhixiang Chen, Xiongxin Zhao, Yichao Lu, Dajiang Zhou, Satoshi Goto. SoCC 2011, 142-145. Web SearchBibTeXDownload |
| 2010 |
|---|
| 2 | An adaptive bandwidth reduction scheme for video coding. Liu Song, Dajiang Zhou, Xin Jin, Satoshi Goto, Peilin Liu. ISCAS 2010, 401-404. Web SearchBibTeXDownload |
| 1 | A Bandwidth Reduction Scheme and Its VLSI Implementation for H.264/AVC Motion Vector Decoding. Jinjia Zhou, Dajiang Zhou, Gang He, Satoshi Goto. PCM (2) 2010, 52-61. Web SearchBibTeXDownload |
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