| 2007 |
|---|
| 19 | Two-level microprocessor-accelerator partitioning. Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid. DATE 2007, 313-318. Web SearchBibTeXDownload |
| 18 | Interactive presentation: Soft-core processor customization using the design of experiments paradigm. David Sheldon, Frank Vahid, Stefano Lonardi. DATE 2007, 821-826. Web SearchBibTeXDownload |
| 17 | A one-shot configurable-cache tuner for improved energy and performance. Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros. DATE 2007, 755-760. Web SearchBibTeXDownload |
| 16 | Clock-frequency assignment for multiple clock domain systems-on-a-chip. Scott Sirowy, Yonghui Wu, Stefano Lonardi, Frank Vahid. DATE 2007, 397-402. Web SearchBibTeXDownload |
| 15 | Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid. FPL 2007, 533-536. Web SearchBibTeXDownload |
| 2006 |
|---|
| 14 | Configurable cache subsetting for fast cache tuning. Pablo Viana, Ann Gordon-Ross, Eamonn J. Keogh, Edna Barros, Frank Vahid. DAC 2006, 695-700. Cited by 8Web SearchBibTeXDownload |
| 13 | A code refinement methodology for performance-improved synthesis from C. Greg Stitt, Frank Vahid, Walid A. Najjar. ICCAD 2006, 716-723. Web SearchBibTeXDownload |
| 2005 |
|---|
| 12 | A highly configurable cache for low energy embedded systems. Chuanjun Zhang, Frank Vahid, Walid A. Najjar. ACM Trans. Embedded Comput. Syst. (4): 363-387 (2005). Web SearchBibTeXDownload |
| 11 | Techniques for synthesizing binaries to an advanced register/memory structure. Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid. FPGA 2005, 118-124. Web SearchBibTeXDownload |
| 10 | A way-halting cache for low-energy high-performance systems. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. TACO (2): 34-54 (2005). Cited by 37Web SearchBibTeXDownload |
| 2004 |
|---|
| 9 | Low Static-Power Frequent-Value Data Caches. Chuanjun Zhang, Jun Yang, Frank Vahid. DATE 2004, 214-219. Cited by 16Web SearchBibTeXDownload |
| 8 | A quantitative analysis of the speedup factors of FPGAs over processors. Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers. FPGA 2004, 162-170. Web SearchBibTeXDownload |
| 7 | A way-halting cache for low-energy high-performance systems. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. ISLPED 2004, 126-131. Cited by 37Web SearchBibTeXDownload |
| 2003 |
|---|
| 6 | First results with eBlocks: embedded systems building blocks. Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh. CODES+ISSS 2003, 168-175. Web SearchBibTeXDownload |
| 5 | A Way-Halting Cache for Low-Energy High-Performance Systems. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. Computer Architecture Letters (2) (2003). Web SearchBibTeXDownload |
| 4 | A Highly-Configurable Cache Architecture for Embedded Systems. Chuanjun Zhang, Frank Vahid, Walid A. Najjar. ISCA 2003, 136-146. Web SearchBibTeXDownload |
| 3 | Energy Benefits of a Configurable Line Size Cache for Embedded Systems. Chuanjun Zhang, Frank Vahid, Walid A. Najjar. ISVLSI 2003, 87-91. Web SearchBibTeXDownload |
| 2 | Profiling tools for hardware/software partitioning of embedded applications. Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt. LCTES 2003, 189-198. Web SearchBibTeXDownload |
| 2002 |
|---|
| 1 | Improving Software Performance with Configurable Logic. Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar. Design Autom. for Emb. Sys. (7): 325-339 (2002). Web SearchBibTeXDownload |
