| 2011 |
|---|
| 9 | Energy-efficient multi-level cell phase-change memory system with data encoding. Jue Wang, Xiangyu Dong, Guangyu Sun, Dimin Niu, Yuan Xie. ICCD 2011, 175-182. Web SearchBibTeXDownload |
| 8 | Moguls: a model to explore the memory hierarchy for bandwidth improvements. Guangyu Sun, Christopher J. Hughes, Changkyu Kim, Jishen Zhao, Cong Xu, Yuan Xie, Yen-Kuang Chen. ISCA 2011, 377-388. Web SearchBibTeXDownload |
| 7 | Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. ISCA 2011, 69-80. Web SearchBibTeXDownload |
| 2010 |
|---|
| 6 | Cost-driven 3D integration with interconnect layers. Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna Das, Yuan Xie, Chita R. Das, Jian Li. DAC 2010, 150-155. Web SearchBibTeXDownload |
| 5 | Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy. IEEE Trans. VLSI Syst. (18): 1621-1624 (2010). Web SearchBibTeXDownload |
| 2009 |
|---|
| 4 | Arithmetic unit design using 180nm TSV-based 3D stacking technology. Jin Ouyang, Guangyu Sun, Yibo Chen, Lian Duan, Tao Zhang, Yuan Xie, Mary Jane Irwin. 3DIC 2009, 1-4. Web SearchBibTeXDownload |
| 3 | A novel architecture of the 3D stacked MRAM L2 cache for CMPs. Guangyu Sun, Xiangyu Dong, Yuan Xie, Jian Li, Yiran Chen. HPCA 2009, 239-249. Web SearchBibTeXDownload |
| 2008 |
|---|
| 2 | A Variation Aware High Level Synthesis Framework. Feng Wang, Guangyu Sun, Yuan Xie. DATE 2008, 1063-1068. Web SearchBibTeXDownload |
| 1 | Thermal-aware Design Considerations for Application-Specific Instruction Set Processor. Hai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam. SASP 2008, 63-68. Web SearchBibTeXDownload |
