| 2011 |
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| 13 | MSV-Driven Floorplanning. Qiang Ma, Zaichen Qian, Evangeline F. Y. Young, Hai Zhou. IEEE Trans. on CAD of Integrated Circuits and Systems (30): 1152-1162 (2011). Web SearchBibTeXDownload |
| 2010 |
|---|
| 12 | Hybrid energy storage system integration for vehicles. Jia Wang, Kun Li, Qin Lv, Hai Zhou, Li Shang. ISLPED 2010, 369-374. Web SearchBibTeXDownload |
| 2009 |
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| 11 | Complete-k-distinguishability for retiming and resynthesis equivalence checking without restricting synthesis. Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee. ASP-DAC 2009, 636-641. Web SearchBibTeXDownload |
| 10 | Statistical reliability analysis under process variation and aging effects. Yinghai Lu, Li Shang, Hai Zhou, Hengliang Zhu, Fan Yang, Xuan Zeng. DAC 2009, 514-519. Web SearchBibTeXDownload |
| 9 | Exception triggered DoS attacks on wireless networks. Yao Zhao, Sagar Vemuri, Jiazhen Chen, Yan Chen, Hai Zhou, Zhi Fu. DSN 2009, 13-22. Web SearchBibTeXDownload |
| 2008 |
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| 8 | A dynamic-programming algorithm for reducing the energy consumption of pipelined System-Level streaming applications. Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee. ASP-DAC 2008, 42-48. Web SearchBibTeXDownload |
| 7 | State space abstraction for parameterized self-stabilizing embedded systems. Nikolaos D. Liveris, Hai Zhou, Robert P. Dick, Prithviraj Banerjee. EMSOFT 2008, 11-20. Web SearchBibTeXDownload |
| 2007 |
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| 6 | Address generation for nanowire decoders. Jia Wang, Ming-Yang Kao, Hai Zhou. ACM Great Lakes Symposium on VLSI 2007, 525-528. Web SearchBibTeXDownload |
| 5 | Retiming for Synchronous Data Flow Graphs. Nikolaos D. Liveris, Chuan Lin, J. Wang, Hai Zhou, Prithviraj Banerjee. ASP-DAC 2007, 480-485. Web SearchBibTeXDownload |
| 4 | Low-Power Optimization by Smart Bit-Width Allocation in a SystemC-Based ASIC Design Environment. Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou. IEEE Trans. on CAD of Integrated Circuits and Systems (26): 447-455 (2007). Web SearchBibTeXDownload |
| 2006 |
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| 3 | Smart bit-width allocation for low power optimization in a systemc based ASIC design environment. Arindam Mallik, Debjit Sinha, Prithviraj Banerjee, Hai Zhou. DATE 2006, 618-623. Web SearchBibTeXDownload |
| 2005 |
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| 2 | An Efficient System-Level to RTL Verification Framework for Computation-Intensive Applications. Nikolaos D. Liveris, Hai Zhou, Prithviraj Banerjee. Asian Test Symposium 2005, 28-33. Web SearchBibTeXDownload |
| 1 | Leakage power optimization with dual-Vth library in high-level synthesis. Xiaoyong Tang, Hai Zhou, Prithviraj Banerjee. DAC 2005, 202-207. Web SearchBibTeXDownload |
