| 2011 |
|---|
| 48 | FPGA Accelerated Parallel Sparse Matrix Factorization for Circuit Simulations. Wei Wu, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang. ARC 2011, 302-315. Web SearchBibTeXDownload |
| 47 | On-chip hybrid power supply system for wireless sensor nodes. Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang. ASP-DAC 2011, 43-48. Web SearchBibTeXDownload |
| 46 | Gemma in April: A matrix-like parallel programming architecture on OpenCL. Tianji Wu, Di Wu, Yu Wang, Xiaorui Zhang, Hong Luo, Ningyi Xu, Huazhong Yang. DATE 2011, 703-708. Web SearchBibTeXDownload |
| 45 | A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis. Yu Wang, Mo Xu, Ling Ren, Xiaorui Zhang, Di Wu, Yong He, Ningyi Xu, Huazhong Yang. ICCAD 2011, 339-344. Web SearchBibTeXDownload |
| 44 | Temperature-Aware NBTI Modeling and the Impact of Standby Leakage Reduction Techniques on Circuit Performance Degradation. Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. IEEE Trans. Dependable Sec. Comput. (8): 756-769 (2011). Web SearchBibTeXDownload |
| 43 | An EScheduler-Based Data Dependence Analysis and Task Scheduling for Parallel Circuit Simulation. Xiaoming Chen, Wei Wu, Yu Wang, Hao Yu, Huazhong Yang. IEEE Trans. on Circuits and Systems (58-II): 702-706 (2011). Web SearchBibTeXDownload |
| 42 | Leakage Power and Circuit Aging Cooptimization by Gate Replacement Techniques. Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. IEEE Trans. VLSI Syst. (19): 615-628 (2011). Web SearchBibTeXDownload |
| 41 | Power Gating Aware Task Scheduling in MPSoC. Yu Wang, Jiang Xu, Yan Xu, Weichen Liu, Huazhong Yang. IEEE Trans. VLSI Syst. (19): 1801-1812 (2011). Web SearchBibTeXDownload |
| 40 | A Low-Power IF Circuit with 5 dB Minimum Input SNR for GFSK Low-IF Receivers. Bo Zhao, Guangming Yu, Tao Chen, Pengpeng Chen, Huazhong Yang, Hui Wang. IEICE Transactions (94-C): 1680-1689 (2011). Web SearchBibTeXDownload |
| 39 | An Energy Efficient Sensor Network Processor with Latency-Aware Adaptive Compression. Yongpan Liu, Shuangchen Li, Jue Wang, Beihua Ying, Huazhong Yang. IEICE Transactions (94-C): 1220-1228 (2011). Web SearchBibTeXDownload |
| 38 | Circuit-level delay modeling considering both TDDB and NBTI. Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Vikas Chandra, Yuchun Ma, Huazhong Yang. ISQED 2011, 14-21. Web SearchBibTeXDownload |
| 2010 |
|---|
| 37 | FPMR: MapReduce framework on FPGA. Yi Shan, Bo Wang, Jing Yan, Yu Wang, Ning-Yi Xu, Huazhong Yang. FPGA 2010, 93-102. Web SearchBibTeXDownload |
| 36 | Making Human Connectome Faster: GPU Acceleration of Brain Network Analysis. Di Wu, Tianji Wu, Yi Shan, Yu Wang, Yong He, Ningyi Xu, Huazhong Yang. ICPADS 2010, 593-600. Web SearchBibTeXDownload |
| 35 | Lightweight Precision-Adaptive Time Synchronization in Wireless Sensor Networks. Li Li, Yongpan Liu, Huazhong Yang, Hui Wang. IEICE Transactions (93-B): 2299-2308 (2010). Web SearchBibTeXDownload |
| 34 | Output remapping technique for critical paths soft-error rate reduction. Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang. IET Computers & Digital Techniques (4): 325-333 (2010). Web SearchBibTeXDownload |
| 33 | A fault-tolerant structure for reliable multi-core systems based on hardware-software co-design. Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang. ISQED 2010, 191-197. Web SearchBibTeXDownload |
| 2009 |
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| 32 | Energy efficient architecture of sensor network node based on compression accelerator. Jue Wang, Beihua Ying, Yongpan Liu, Huazhong Yang, Hui Wang. ACM Great Lakes Symposium on VLSI 2009, 117-120. Web SearchBibTeXDownload |
| 31 | A case study of on-chip sensor network in multiprocessor system-on-chip. Yu Wang, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang. CASES 2009, 241-250. Web SearchBibTeXDownload |
| 30 | A Fault-tolerant Structure for Reliable Multi-core Systems Based on Hardware-Software Co-design. Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang. CoRR (abs/0910.3736) (2009). Web SearchBibTeXDownload |
| 29 | Gate replacement techniques for simultaneous leakage and aging optimization. Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang. DATE 2009, 328-333. Web SearchBibTeXDownload |
| 28 | Temperature-Aware NBTI Modeling Techniques in Digital Circuits. Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie. IEICE Transactions (92-C): 875-886 (2009). Web SearchBibTeXDownload |
| 27 | Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang. ISLPED 2009, 39-44. Web SearchBibTeXDownload |
| 26 | On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang. ISQED 2009, 19-26. Web SearchBibTeXDownload |
| 25 | On-line MPSoC Scheduling Considering Power Gating Induced Power/Ground Noise. Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang. ISVLSI 2009, 109-114. Web SearchBibTeXDownload |
| 24 | Leakage Power Reduction through Dual Vth Assignment Considering Threshold voltage Variation. Yu Wang, Xukai Shen, Rong Luo, Huazhong Yang. Journal of Circuits, Systems, and Computers (18): 1243-1261 (2009). Web SearchBibTeXDownload |
| 2008 |
|---|
| 23 | A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in UDVS application. Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang. ASP-DAC 2008, 304-309. Web SearchBibTeXDownload |
| 22 | Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits. Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang. IEEE Trans. VLSI Syst. (16): 1101-1113 (2008). Web SearchBibTeXDownload |
| 21 | Output Remapping Technique for Soft-Error Rate Reduction in Critical Paths. Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang. ISQED 2008, 74-77. Web SearchBibTeXDownload |
| 20 | Implementation of low-swing differential interface circuits for high-speed on-chip asynchronous interconnection. Fei Qiao, Huazhong Yang, Gang Huang, Hui Wang. Science in China Series F: Information Sciences (51): 975-984 (2008). Web SearchBibTeXDownload |
| 19 | Design of Signal Constellations in the Presence of Phase Noise. Yang Li, Shuzheng Xu, Huazhong Yang. VTC Fall 2008, 1-5. Web SearchBibTeXDownload |
| 2007 |
|---|
| 18 | Temperature-aware NBTI modeling and the impact of input vector control on performance degradation. Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. DATE 2007, 546-551. Web SearchBibTeXDownload |
| 17 | A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor Pairs. Shaohua Wang, Jinguo Quan, Rong Luo, Hao Cheng, Huazhong Yang. ISCAS 2007, 937-940. Web SearchBibTeXDownload |
| 16 | Thermal vs Energy Optimization for DVFS-Enabled Processors in Embedded Systems. Yongpan Liu, Huazhong Yang, Robert P. Dick, Hui Wang, Li Shang. ISQED 2007, 204-209. Web SearchBibTeXDownload |
| 15 | Modeling of PMOS NBTI Effect Considering Temperature Variation. Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. ISQED 2007, 139-144. Web SearchBibTeXDownload |
| 14 | Modified Conditional-Precharge Sense-amplifier-Based Flip-Flop with Improved Speed. Fei Qiao, Huazhong Yang, Dingli Wei, Hui Wang. Journal of Circuits, Systems, and Computers (16): 199-210 (2007). Web SearchBibTeXDownload |
| 13 | A Novel Gate-Level NBTI Delay Degradation Model with Stacking Effect. Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie. PATMOS 2007, 160-170. Web SearchBibTeXDownload |
| 12 | Phase noise analysis of oscillators with Sylvester representation for periodic time-varying modulus matrix by regular perturbations. JianXing Fan, Huazhong Yang, Hui Wang, Xiaolang Yan, Chaohuan Hou. Science in China Series F: Information Sciences (50): 587-599 (2007). Web SearchBibTeXDownload |
| 2006 |
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| 11 | Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate. Yu Wang, Hui Wang, Huazhong Yang. APCCAS 2006, 964-967. Web SearchBibTeXDownload |
| 10 | A 0.9V 10GHz 71µW Static D Flip-flop by using FinFET Devices. Saihua Lin, Rong Luo, Huazhong Yang, Hui Wang. APCCAS 2006, 1795-1798. Web SearchBibTeXDownload |
| 9 | Genetic Algorithm Based Fine-Grain Sleep Transistor Insertion Technique for Leakage Optimization. Yu Wang, Yongpan Liu, Rong Luo, Huazhong Yang. ICNC (1) 2006, 716-725. Web SearchBibTeXDownload |
| 8 | Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits. Yu Wang, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang. ISLPED 2006, 238-243. Web SearchBibTeXDownload |
| 7 | Simultaneous Fine-grain Sleep Transistor Placement and Sizing for Leakage Optimization. Yu Wang, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang. ISQED 2006, 723-728. Web SearchBibTeXDownload |
| 6 | Signal-Path-Level Dual-VT Assignment for Leakage Power Reduction. Yu Wang, Huazhong Yang, Hui Wang. Journal of Circuits, Systems, and Computers (15): 197-216 (2006). Web SearchBibTeXDownload |
| 5 | IR-drop Reduction Through Combinational Circuit Partitioning. Hai Lin, Yu Wang, Rong Luo, Huazhong Yang, Hui Wang. PATMOS 2006, 370-381. Web SearchBibTeXDownload |
| 4 | A Low Power ROM-Less Direct Digital Frequency Synthesizer with Preset Value Pipelined Accumulator. Jun Chen, Rong Luo, Huazhong Yang, Hui Wang. VLSI Design 2006, 377-380. Web SearchBibTeXDownload |
| 2005 |
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| 3 | A Hierarchical Approach for Incremental Floorplan Based on Genetic Algorithms. Yongpan Liu, Huazhong Yang, Rong Luo, Hui Wang. ICNC (3) 2005, 219-224. Web SearchBibTeXDownload |
| 2 | Improved Multiuser Detection for Fast FH/MFSK Systems. Hui Zhang, Huazhong Yang, Shuzheng Xu, Hui Wang. ICWN 2005, 130-136. Web SearchBibTeX |
| 1999 |
|---|
| 1 | An SA-Based Nonlinear Function Synthesizer for Linear Analog Integrated Circuits. Huazhong Yang, Rong Luo, Hui Wang, Runsheng Liu. ASP-DAC 1999, 9. Web SearchBibTeXDownload |
