| 2011 |
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| 15 | Modeling and implementation of classification rule discovery by ant colony optimisation for spatial land-use suitability assessment. Jia Yu, Yun Chen, Jianping Wu. Computers, Environment and Urban Systems (35): 308-319 (2011). Web SearchBibTeXDownload |
| 14 | Embedding meshes into twisted-cubes. Xi Wang, Jianxi Fan, Xiaohua Jia, Shukui Zhang, Jia Yu. Inf. Sci. (181): 3085-3099 (2011). Web SearchBibTeXDownload |
| 13 | Efficient unicast in bijective connection networks with the restricted faulty node set. Jianxi Fan, Xiaohua Jia, Xin Liu, Shukui Zhang, Jia Yu. Inf. Sci. (181): 2303-2315 (2011). Web SearchBibTeXDownload |
| 12 | Cellular automata-based spatial multi-criteria land suitability simulation for irrigated agriculture. Jia Yu, Yun Chen, Jianping Wu, Shahbaz Khan. International Journal of Geographical Information Science (25): 131-148 (2011). Web SearchBibTeXDownload |
| 11 | An efficient fault-tolerant routing algorithm in bijective connection networks with restricted faulty edges. Jianxi Fan, Xiaohua Jia, Baolei Cheng, Jia Yu. Theor. Comput. Sci. (412): 3440-3450 (2011). Web SearchBibTeXDownload |
| 2010 |
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| 10 | Experience on Applying Push Model to Packet Processors in High Performance Routers. Bo Yuan, Hongbo Zhao, Chengchen Hu, Bin Liu, Jia Yu, Laxmi N. Bhuyan. GLOBECOM 2010, 1-5. Web SearchBibTeXDownload |
| 2008 |
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| 9 | Revisiting the Cache Effect on Multicore Multithreaded Network Processors. Zhen Liu, Jia Yu, Xiaojun Wang, Bin Liu, Laxmi N. Bhuyan. DSD 2008, 317-324. Web SearchBibTeXDownload |
| 2007 |
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| 8 | Assertion-Based Design Exploration of DVS in Network Processor Architectures. Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin. CoRR (abs/0710.4714) (2007). Web SearchBibTeXDownload |
| 7 | Program Mapping onto Network Processors by Recursive Bipartitioning and Refining. Jia Yu, Jingnan Yao, Laxmi N. Bhuyan, Jun Yang. DAC 2007, 805-810. Web SearchBibTeXDownload |
| 6 | Security Analysis and Improvement of a ($t, n$) Threshold Proxy Signature Scheme. Fanyu Kong, Jia Yu, Baodong Qin, Ming Li, Daxing Li. SNPD (3) 2007, 923-926. Web SearchBibTeXDownload |
| 5 | Conserving network processor power consumption by exploiting traffic variability. Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan. TACO (4) (2007). Web SearchBibTeXDownload |
| 2005 |
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| 4 | Low power network processor design using clock gating. Yan Luo, Jia Yu, Jun Yang, Laxmi N. Bhuyan. DAC 2005, 712-715. Cited by 14Web SearchBibTeXDownload |
| 3 | Assertion-Based Design Exploration of DVS in Network Processor Architectures. Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang, Felice Balarin. DATE 2005, 92-97. Web SearchBibTeXDownload |
| 2 | Enhancing Network Processor Simulation Speed with Statistical Input Sampling. Jia Yu, Jun Yang, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan. HiPEAC 2005, 68-83. Web SearchBibTeXDownload |
| 1 | A low energy cache design for multimedia applications exploiting set access locality. Jun Yang, Jia Yu, Youtao Zhang. Journal of Systems Architecture (51): 653-664 (2005). Web SearchBibTeXDownload |
