Kai Ma
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- Sorted by Year/Conf, Year/Citation, Citation
| 2011 | ||
|---|---|---|
| 5 | DPPC: Dynamic power partitioning and capping in chip multiprocessors. Kai Ma, Xiaorui Wang, Yefu Wang. ICCD 2011, 39-44. Web SearchBibTeXDownload | |
| 4 | Adaptive Power Control with Online Model Estimation for Chip Multiprocessors. Xiaorui Wang, Kai Ma, Yefu Wang. IEEE Trans. Parallel Distrib. Syst. (22): 1681-1696 (2011). Web SearchBibTeXDownload | |
| 3 | Scalable power control for many-core architectures running multi-threaded applications. Kai Ma, Xue Li, Ming Chen, Xiaorui Wang. ISCA 2011, 449-460. Web SearchBibTeXDownload | |
| 2010 | ||
| 2 | Achieving Fair or Differentiated Cache Sharing in Power-Constrained Chip Multiprocessors. Xiaorui Wang, Kai Ma, Yefu Wang. ICPP 2010, 1-10. Web SearchBibTeXDownload | |
| 2009 | ||
| 1 | Temperature-constrained power control for chip multiprocessors with online model estimation. Yefu Wang, Kai Ma, Xiaorui Wang. ISCA 2009, 314-324. Web SearchBibTeXDownload | |
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