Narayanan Vijaykrishnan

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2012
258Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling. Shengqi Yang, Pallav Gupta, Marilyn Wolf, Dimitrios N. Serpanos, Vijaykrishnan Narayanan, Yuan Xie. ACM Trans. Embedded Comput. Syst. (11): 62 (2012). Web SearchBibTeXDownload
257Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores. Emre Kultursay, Karthik Swaminathan, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta. CODES+ISSS 2012, 245-254. Web SearchBibTeXDownload
256Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs. Adwait Jog, Asit K. Mishra, Cong Xu, Yuan Xie, Vijaykrishnan Narayanan, Ravishankar Iyer, Chita R. Das. DAC 2012, 243-252. Web SearchBibTeXDownload
255Accelerating neuromorphic vision algorithms for recognition. Ahmed Al-Maashri, Michael DeBole, Matthew Cotter, Nandhini Chandramoorthy, Yang Xiao, Vijaykrishnan Narayanan, Chaitali Chakrabarti. DAC 2012, 579-584. Web SearchBibTeXDownload
254An FPGA-based accelerator for cortical object classification. Sun-Mi Park, Srinidhi Kestur, Jagdish Sabarad, Vijaykrishnan Narayanan, Mary Jane Irwin. DATE 2012, 691-696. Web SearchBibTeXDownload
253Design space exploration of workload-specific last-level caches. Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir. ISLPED 2012, 243-248. Web SearchBibTeXDownload
252Ultra Low Power Circuit Design Using Tunnel FETs. Ravindhiran Mukundrajan, Matthew Cotter, Vinay Saripalli, Mary Jane Irwin, Suman Datta, Vijaykrishnan Narayanan. ISVLSI 2012, 153-158. Web SearchBibTeXDownload
2011
251Variation-Aware Task and Communication Mapping for MPSoC Architecture. Feng Wang, Yibo Chen, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan. IEEE Trans. on CAD of Integrated Circuits and Systems (30): 295-307 (2011). Web SearchBibTeXDownload
250A case for heterogeneous on-chip interconnects for CMPs. Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das. ISCA 2011, 389-400. Web SearchBibTeXDownload
249Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs. Asit K. Mishra, Xiangyu Dong, Guangyu Sun, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. ISCA 2011, 69-80. Web SearchBibTeXDownload
248Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores. Karthik Swaminathan, Emre Kultursay, Vinay Saripalli, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Suman Datta. ISLPED 2011, 247-252. Web SearchBibTeXDownload
247RAFT: A router architecture with frequency tuning for on-chip networks. Asit K. Mishra, Aditya Yanamandra, Reetuparna Das, Soumya Eachempati, Ravi R. Iyer, Narayanan Vijaykrishnan, Chita R. Das. J. Parallel Distrib. Comput. (71): 625-640 (2011). Web SearchBibTeXDownload
2010
246Optimizing power and performance for reliable on-chip networks. Aditya Yanamandra, Soumya Eachempati, Niranjan Soundararajan, Vijaykrishnan Narayanan, Mary Jane Irwin, Ramakrishnan Krishnan. ASP-DAC 2010, 431-436. Web SearchBibTeXDownload
245A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications. J. Singh, Krishnan Ramakrishnan, S. Mookerjea, Suman Datta, Narayanan Vijaykrishnan, D. K. Pradhan. ASP-DAC 2010, 181-186. Web SearchBibTeXDownload
244Investigating the impact of NBTI on different power saving cache strategies. Andrew J. Ricketts, J. Singh, Krishnan Ramakrishnan, Narayanan Vijaykrishnan, D. K. Pradhan. DATE 2010, 592-597. Web SearchBibTeXDownload
243A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching. Aditi Rathi, Michael DeBole, Weina Ge, Robert T. Collins, Narayanan Vijaykrishnan. DATE 2010, 172-177. Web SearchBibTeXDownload
242Thermal Gradient Aware Clock Skew Scheduling for FPGAs. Sungmin Bae, Narayanan Vijaykrishnan. FPL 2010, 101-106. Web SearchBibTeXDownload
241On the Effects of Process Variation in Network-on-Chip Architectures. Chrysostomos Nicopoulos, Suresh Srinivasan, Aditya Yanamandra, Dongkook Park, Vijaykrishnan Narayanan, Chita R. Das, Mary Jane Irwin. IEEE Trans. Dependable Sec. Comput. (7): 240-254 (2010). Web SearchBibTeXDownload
240A Scalable Bandwidth Aware Architecture for Connected Component Labeling. Vikram Sampath Kumar, Kevin M. Irick, Ahmed Al-Maashri, Narayanan Vijaykrishnan. ISVLSI 2010, 116-121. Web SearchBibTeXDownload
239Total Power Optimization for Combinational Logic Using Genetic Algorithms. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. Signal Processing Systems (58): 145-160 (2010). Web SearchBibTeXDownload
2009
238Compiler-assisted soft error detection under performance and energy constraints in embedded systems. Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. ACM Trans. Embedded Comput. Syst. (8) (2009). Web SearchBibTeXDownload
237A framework for estimating NBTI degradation of microarchitectural components. Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan. ASP-DAC 2009, 455-460. Web SearchBibTeXDownload
236Exploiting clock skew scheduling for FPGA. Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijaykrishnan. DATE 2009, 1524-1529. Web SearchBibTeXDownload
235In-Network Caching for Chip Multiprocessors. Aditya Yanamandra, Mary Jane Irwin, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Sri Hari Krishna Narayanan. HiPEAC 2009, 373-388. Web SearchBibTeXDownload
234Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs. Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das. HPCA 2009, 175-186. Web SearchBibTeXDownload
233An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization. Jungsub Kim, Lanping Deng, Prasanth Mangalagiri, Kevin M. Irick, Kanwaldeep Sobti, Mahmut T. Kandemir, Vijaykrishnan Narayanan, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun. IEEE Trans. Computers (58): 1654-1667 (2009). Web SearchBibTeXDownload
232Process-Variation-Aware Adaptive Cache Architecture and Management. Madhu Mutyam, Feng Wang, Krishnan Ramakrishnan, Vijaykrishnan Narayanan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin. IEEE Trans. Computers (58): 865-877 (2009). Web SearchBibTeXDownload
231Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits. Rajaraman Ramanarayanan, Vijay Degalahal, Krishnan Ramakrishnan, Jungsub Kim, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Kenan Unlu. IEEE Trans. Dependable Sec. Comput. (6): 202-216 (2009). Web SearchBibTeXDownload
230Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect. Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud. IET Circuits, Devices & Systems (3): 64-75 (2009). Web SearchBibTeXDownload
229Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies. Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir. IJDSN (5): 209-223 (2009). Web SearchBibTeXDownload
228New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components. Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan. International Journal of Parallel Programming (37): 417-431 (2009). Web SearchBibTeXDownload
227A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications. Sungmin Bae, Krishnan Ramakrishnan, Narayanan Vijaykrishnan. ISVLSI 2009, 193-198. Web SearchBibTeXDownload
226A case for dynamic frequency tuning in on-chip networks. Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar Iyer, Narayanan Vijaykrishnan, Chita R. Das. MICRO 2009, 292-303. Web SearchBibTeXDownload
2008
225A low-power phase change memory based hybrid cache architecture. Prasanth Mangalagiri, Karthik Sarpatwari, Aditya Yanamandra, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin, Osama Awadel Karim. ACM Great Lakes Symposium on VLSI 2008, 395-398. Web SearchBibTeXDownload
224Analysis and solutions to issue queue process variation. Niranjan Soundararajan, Aditya Yanamandra, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin. DSN 2008, 11-21. Web SearchBibTeXDownload
223Performance and power optimization through data compression in Network-on-Chip architectures. Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar Iyer, Mazin S. Yousif, Chita R. Das. HPCA 2008, 215-225. Web SearchBibTeXDownload
222Comparative analysis of NBTI effects on low power and high performance flip-flops. Krishnan Ramakrishnan, Xiaoxia Wu, Narayanan Vijaykrishnan, Yuan Xie. ICCD 2008, 200-205. Web SearchBibTeXDownload
221Toward Increasing FPGA Lifetime. Suresh Srinivasan, Krishnan Ramakrishnan, Prasanth Mangalagiri, Yuan Xie, Vijaykrishnan Narayanan, Mary Jane Irwin, Karthik Sarpatwari. IEEE Trans. Dependable Sec. Comput. (5): 115-127 (2008). Web SearchBibTeXDownload
220Design Space Exploration for 3-D Cache. Yuh-Fang Tsai, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. IEEE Trans. VLSI Syst. (16): 444-455 (2008). Web SearchBibTeXDownload
219Case Study of Reliability-Aware and Low-Power Design. Shengqi Yang, Wenping Wang, Tiehan Lv, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie. IEEE Trans. VLSI Syst. (16): 861-873 (2008). Web SearchBibTeXDownload
218Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues. Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arifur Rahman. IEEE Trans. VLSI Syst. (16): 882-893 (2008). Web SearchBibTeXDownload
217Exploring architectural solutions for energy optimisations in bus-based system-on-chip. Suresh Srinivasan, Lin Li, Martino Ruggiero, Federico Angiolini, Narayanan Vijaykrishnan, Luca Benini. IET Computers & Digital Techniques (2): 347-354 (2008). Web SearchBibTeXDownload
216MIRA: A Multi-layered On-Chip Interconnect Router Architecture. Dongkook Park, Soumya Eachempati, Reetuparna Das, Asit K. Mishra, Yuan Xie, Narayanan Vijaykrishnan, Chita R. Das. ISCA 2008, 251-261. Web SearchBibTeXDownload
215Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures. Niranjan Soundararajan, Narayanan Vijaykrishnan, Anand Sivasubramaniam. ISLPED 2008, 351-356. Web SearchBibTeXDownload
214Hierarchical Soft Error Estimation Tool (HSEET). Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin, K. Unlu. ISQED 2008, 680-683. Web SearchBibTeXDownload
2007
213Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. Greg M. Link, Narayanan Vijaykrishnan. CoRR (abs/0710.4764) (2007). Web SearchBibTeXDownload
212Thermal-Aware Task Allocation and Scheduling for Embedded Systems. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. CoRR (abs/0710.4660) (2007). Web SearchBibTeXDownload
211Leakage-Aware Interconnect for On-Chip Network. Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin. CoRR (abs/0710.4731) (2007). Web SearchBibTeXDownload
210Thermally robust clocking schemes for 3D integrated circuits. Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud. DATE 2007, 1206-1211. Web SearchBibTeXDownload
209Assessing carbon nanotube bundle interconnect for future FPGA architectures. Soumya Eachempati, Arthur Nieuwoudt, Aman Gayasen, Narayanan Vijaykrishnan, Yehia Massoud. DATE 2007, 307-312. Web SearchBibTeXDownload
208Working with process variation aware caches. Madhu Mutyam, Narayanan Vijaykrishnan. DATE 2007, 1152-1157. Web SearchBibTeXDownload
207TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms. Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijay Narayanan, K. Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun. FPL 2007, 68-73. Web SearchBibTeXDownload
206Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects. Dongkook Park, Reetuparna Das, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Ravishankar R. Iyer, Chita R. Das. Hot Interconnects 2007, 15-20. Web SearchBibTeXDownload
205Variation-aware task allocation and scheduling for MPSoC. Feng Wang, Chrysostomos Nicopoulos, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan. ICCAD 2007, 598-603. Web SearchBibTeXDownload
204FPGA routing architecture analysis under variations. Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan. ICCD 2007, 152-157. Web SearchBibTeXDownload
203On the Detection of Clones in Sensor Networks Using Random Key Predistribution. Richard R. Brooks, P. Y. Govindaraju, Matthew Pirretti, Narayanan Vijaykrishnan, Mahmut T. Kandemir. IEEE Transactions on Systems, Man, and Cybernetics, Part C (37): 1246-1258 (2007). Web SearchBibTeXDownload
202OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems. Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio. IEEE Trans. Computers (56): 2-17 (2007). Web SearchBibTeXDownload
201On-chip bus thermal analysis and optimisation. Feng Wang, Michael DeBole, Xiaoxia Wu, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. IET Computers & Digital Techniques (1): 590-599 (2007). Web SearchBibTeXDownload
200Optimising power efficiency in trace cache fetch unit. Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir. IET Computers & Digital Techniques (1): 334-348 (2007). Web SearchBibTeXDownload
199Design of power-aware FPGA fabrics. Aman Gayasen, Suresh Srinivasan, Narayanan Vijaykrishnan, Mahmut T. Kandemir. IJES (3): 52-64 (2007). Web SearchBibTeXDownload
198A novel dimensionally-decomposed router for on-chip communication in 3D architectures. Jongman Kim, Chrysostomos Nicopoulos, Dongkook Park, Reetuparna Das, Yuan Xie, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das. ISCA 2007, 138-149. Web SearchBibTeXDownload
197Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers. Mosin Mondal, Andrew J. Ricketts, Sami Kirolos, Tamer Ragheb, Greg M. Link, Narayanan Vijaykrishnan, Yehia Massoud. ISQED 2007, 67-72. Web SearchBibTeXDownload
196Variation Analysis of CAM Cells. Amol Mupid, Madhu Mutyam, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. ISQED 2007, 333-338. Web SearchBibTeXDownload
195Variation Impact on SER of Combinational Circuits. Krishnan Ramakrishnan, R. Rajaraman, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. ISQED 2007, 911-916. Web SearchBibTeXDownload
194Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures. Soumya Eachempati, Narayanan Vijaykrishnan, Arthur Nieuwoudt, Yehia Massoud. ISVLSI 2007, 516-517. Web SearchBibTeXDownload
193Investigating Simple Low Latency Reliable Multiported Register Files. Andrew J. Ricketts, Madhu Mutyam, Narayanan Vijaykrishnan, Mary Jane Irwin. ISVLSI 2007, 375-382. Web SearchBibTeXDownload
192Reducing non-deterministic loads in low-power caches via early cache set resolution. Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin. Microprocessors and Microsystems (31): 293-301 (2007). Web SearchBibTeXDownload
191Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations. K. Sobti, Lanping Deng, Chaitali Chakrabarti, Nikos Pitsianis, Xiaobai Sun, Jungsub Kim, Prasanth Mangalagiri, Kevin M. Irick, Mahmut T. Kandemir, Vijay Narayanan. SiPS 2007, 463-468. Web SearchBibTeXDownload
190Impact of NBTI on FPGAs. Krishnan Ramakrishnan, Sivaprakasam Suresh, Narayanan Vijaykrishnan, Mary Jane Irwin. VLSI Design 2007, 717-722. Web SearchBibTeXDownload
189Architecting Microprocessor Components in 3D Design Space. Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. VLSI Design 2007, 103-108. Web SearchBibTeXDownload
188Reliability-aware Co-synthesis for Embedded Systems. Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. VLSI Signal Processing (49): 87-99 (2007). Web SearchBibTeXDownload
2006
187Reducing dynamic and leakage energy in VLIW architectures. Wei Zhang, Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. ACM Trans. Embedded Comput. Syst. (5): 1-28 (2006). Web SearchBibTeXDownload
186Leakage Optimized DECAP Design for FPGAs. Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie, Narayanan Vijaykrishnan, Rong Luo. APCCAS 2006, 960-963. Web SearchBibTeXDownload
185Object duplication for improving reliability. Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. ASP-DAC 2006, 140-145. Web SearchBibTeXDownload
184FLAW: FPGA lifetime awareness. Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie, Narayanan Vijaykrishnan, Karthik Sarpatwari. DAC 2006, 630-635. Web SearchBibTeXDownload
183Priority scheduling in digital microfluidics-based biochips. Andrew J. Ricketts, Kevin M. Irick, Narayanan Vijaykrishnan, Mary Jane Irwin. DATE 2006, 329-334. Web SearchBibTeXDownload
182On-chip bus thermal analysis and optimization. Feng Wang, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. DATE 2006, 850-855. Web SearchBibTeXDownload
181Exploring Fault-Tolerant Network-on-Chip Architectures. Dongkook Park, Chrysostomos Nicopoulos, Jongman Kim, Narayanan Vijaykrishnan, Chita R. Das. DSN 2006, 93-104. Web SearchBibTeXDownload
180Switch Box Architectures for Three-Dimensional FPGAs. Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman. FCCM 2006, 335-336. Web SearchBibTeXDownload
179Thermal characterization and optimization in platform FPGAs. Priya Sundararajan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan. ICCAD 2006, 443-447. Web SearchBibTeXDownload
178Reliability Concerns in Embedded System Designs. Narayanan Vijaykrishnan, Yuan Xie. IEEE Computer (39): 118-120 (2006). Web SearchBibTeXDownload
177Block-based frequency scalable technique for efficient hierarchical coding. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli. IEEE Transactions on Signal Processing (54): 2559-2566 (2006). Web SearchBibTeXDownload
176An efficient architecture for motion estimation and compensation in the transform domain. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf. IEEE Trans. Circuits Syst. Video Techn. (16): 191-201 (2006). Web SearchBibTeXDownload
175Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin. IEEE Trans. Circuits Syst. Video Techn. (16): 655-662 (2006). Web SearchBibTeXDownload
174The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense. Matthew Pirretti, Sencun Zhu, Narayanan Vijaykrishnan, Patrick McDaniel, Mahmut T. Kandemir, Richard R. Brooks. IJDSN (2): 267-287 (2006). Web SearchBibTeXDownload
173Design and Management of 3D Chip Multiprocessors Using Network-in-Memory. Feihui Li, Chrysostomos Nicopoulos, Thomas D. Richardson, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir. ISCA 2006, 130-141. Web SearchBibTeXDownload
172Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada. ISQED 2006, 775-780. Web SearchBibTeXDownload
171Thermal Trends in Emerging Technologies. Greg M. Link, Narayanan Vijaykrishnan. ISQED 2006, 625-632. Web SearchBibTeXDownload
170Interconnect and Thermal-aware Floorplanning for 3D Microprocessors. Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. ISQED 2006, 98-104. Web SearchBibTeXDownload
169A Parallel Architecture for Hardware Face Detection. Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin. ISVLSI 2006, 452-453. Web SearchBibTeXDownload
168Variation Aware Placement for FPGAs. Suresh Srinivasan, Narayanan Vijaykrishnan. ISVLSI 2006, 422-423. Web SearchBibTeXDownload
167Delay and Energy Efficient Data Transmission for On-Chip Buses. Madhu Mutyam, Melvin Eze, Narayanan Vijaykrishnan, Yuan Xie. ISVLSI 2006, 355-360. Web SearchBibTeXDownload
166Reliability-Aware SOC Voltage Islands Partition and Floorplan. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie. ISVLSI 2006, 343-348. Web SearchBibTeXDownload
165Compiler-directed thermal management for VLIW functional units. Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. LCTES 2006, 163-172. Web SearchBibTeXDownload
164ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers. Chrysostomos Nicopoulos, Dongkook Park, Jongman Kim, Narayanan Vijaykrishnan, Mazin S. Yousif, Chita R. Das. MICRO 2006, 333-346. Web SearchBibTeXDownload
163Process Variation Aware Parallelization Strategies for MPSoCs. Suresh Srinivasan, Raghavan Ramadoss, Narayanan Vijaykrishnan. SoCC 2006, 179-182. Web SearchBibTeXDownload
162Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs. Priya Sundararajan, Sridhar Krishnamurthy, Narayanan Vijaykrishnan, Kamal Chaudhary, Rajeev Jayaraman. SoCC 2006, 105-106. Web SearchBibTeXDownload
161A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks. Thomas D. Richardson, Chrysostomos Nicopoulos, Dongkook Park, Narayanan Vijaykrishnan, Yuan Xie, Chita R. Das, Vijay Degalahal. VLSI Design 2006, 657-664. Web SearchBibTeXDownload
160SEAT-LA: A Soft Error Analysis Tool for Combinational Logic. R. Rajaraman, J. S. Kim, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. VLSI Design 2006, 499-502. Web SearchBibTeXDownload
2005
159Compiler-directed high-level energy estimation and optimization. Ismail Kadayif, Mahmut T. Kandemir, Guilin Chen, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam. ACM Trans. Embedded Comput. Syst. (4): 819-850 (2005). Web SearchBibTeXDownload
158Analyzing data reuse for cache reconfiguration. Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. ACM Trans. Embedded Comput. Syst. (4): 851-876 (2005). Web SearchBibTeXDownload
157Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip. Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin. Advances in Computers (63): 36-92 (2005). Web SearchBibTeXDownload
156Design and analysis of an NoC architecture from performance, reliability and energy perspective. Jongman Kim, Dongkook Park, Chrysostomos Nicopoulos, Narayanan Vijaykrishnan, Chita R. Das. ANCS 2005, 173-182. Web SearchBibTeXDownload
155Low-leakage robust SRAM cell design for sub-100nm technologies. Shengqi Yang, Wayne Wolf, Wenping Wang, Narayanan Vijaykrishnan, Yuan Xie. ASP-DAC 2005, 539-544. Web SearchBibTeXDownload
154Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan. ASP-DAC 2005, 1200-1203. Web SearchBibTeXDownload
153Leakage control in FPGA routing fabric. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Tim Tuan. ASP-DAC 2005, 661-664. Web SearchBibTeXDownload
152Designing reliable circuit in the presence of soft errors. Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. ASP-DAC 2005, 1. Web SearchBibTeXDownload
151A low latency router supporting adaptivity for on-chip interconnects. Jongman Kim, Dongkook Park, Theo Theocharides, Narayanan Vijaykrishnan, Chita R. Das. DAC 2005, 559-564. Web SearchBibTeXDownload
150Exploring technology alternatives for nano-scale FPGA interconnects. Aman Gayasen, Narayanan Vijaykrishnan, Mary Jane Irwin. DAC 2005, 921-926. Web SearchBibTeXDownload
149Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Dimitrios N. Serpanos, Yuan Xie. DATE 2005, 64-69. Web SearchBibTeXDownload
148Leakage-Aware Interconnect for On-Chip Network. Yuh-Fang Tsai, Vijaykrishnan Narayanan, Yuan Xie, Mary Jane Irwin. DATE 2005, 230-231. Web SearchBibTeXDownload
147Thermal-Aware Task Allocation and Scheduling for Embedded Systems. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. DATE 2005, 898-899. Web SearchBibTeXDownload
146Compiler-Directed Instruction Duplication for Soft Error Detection. Jie S. Hu, Feihui Li, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. DATE 2005, 1056-1057. Web SearchBibTeXDownload
145Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures. Suresh Srinivasan, Lin Li, Narayanan Vijaykrishnan. DATE 2005, 218-223. Web SearchBibTeXDownload
144Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip. Greg M. Link, Narayanan Vijaykrishnan. DATE 2005, 648-649. Web SearchBibTeXDownload
143Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only). E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan. FPGA 2005, 265. Web SearchBibTeXDownload
142Temperature-Aware Voltage Islands Architecting in System-on-Chip Design. Wei-Lun Hung, Greg M. Link, Yuan Xie, Narayanan Vijaykrishnan, Nagu R. Dhanwada, John Conner. ICCD 2005, 689-696. Web SearchBibTeXDownload
141Three-Dimensional Cache Design Exploration Using 3DCacti. Yuh-Fang Tsai, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. ICCD 2005, 519-524. Web SearchBibTeXDownload
140Analysis of Error Recovery Schemes for Networks on Chips. Srinivasan Murali, Theo Theocharides, Narayanan Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli. IEEE Design & Test of Computers (22): 434-442 (2005). Web SearchBibTeXDownload
139A Holistic Approach to Designing Energy-Efficient Cluster Interconnects. Eun Jung Kim, Greg M. Link, Ki Hwan Yum, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Chita R. Das. IEEE Trans. Computers (54): 660-671 (2005). Web SearchBibTeXDownload
138Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan. IEEE Trans. Computers (54): 714-726 (2005). Web SearchBibTeXDownload
137Soft errors issues in low-power caches. Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. IEEE Trans. VLSI Syst. (13): 1157-1166 (2005). Web SearchBibTeXDownload
136Improving Java performance using dynamic method migration on FPGAs. Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo. IJES (1): 228-236 (2005). Web SearchBibTeXDownload
135Symmetric encryption in reconfigurable and custom hardware. Eric J. Swankoski, Narayanan Vijaykrishnan, Richard R. Brooks, Mahmut T. Kandemir, Mary Jane Irwin. IJES (1): 205-217 (2005). Web SearchBibTeXDownload
134Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan. IPDPS 2005. Web SearchBibTeXDownload
133Thermal-Aware Floorplanning Using Genetic Algorithms. Wei-Lun Hung, Yuan Xie, Narayanan Vijaykrishnan, Charles Addo-Quaye, Theo Theocharides, Mary Jane Irwin. ISQED 2005, 634-639. Web SearchBibTeXDownload
132High Performance Array Processor for Video Decoding. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin. ISVLSI 2005, 28-33. Web SearchBibTeXDownload
131A Data-Driven Approach for Embedded Security. Hendra Saputra, Ozcan Ozturk, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Richard R. Brooks. ISVLSI 2005, 104-109. Web SearchBibTeXDownload
130Soft errors: is the concern for soft-errors overblown?. Narayanan Vijaykrishnan. ITC 2005, 2. Web SearchBibTeXDownload
129An integer linear programming-based tool for wireless sensor networks. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. J. Parallel Distrib. Comput. (65): 247-260 (2005). Web SearchBibTeXDownload
128Simultaneous memory and bus partitioning for SoC architectures. Suresh Srinivasan, Federico Angiolini, Martino Ruggiero, Luca Benini, Narayanan Vijaykrishnan. SoCC 2005, 125-128. Web SearchBibTeXDownload
127Implementing LDPC Decoding on Network-on-Chip. Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin. VLSI Design 2005, 134-137. Web SearchBibTeXDownload
126Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty. Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. VLSI Design 2005, 374-379. Web SearchBibTeXDownload
125A Nanosensor Array-Based VLSI Gas Discriminator. Kevin M. Irick, Wei Xu, Narayanan Vijaykrishnan, Mary Jane Irwin. VLSI Design 2005, 241-246. Web SearchBibTeXDownload
124Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs. E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti, Narayanan Vijaykrishnan. VLSI Design 2005, 736-741. Web SearchBibTeXDownload
123Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan, Yuan Xie, Wenping Wang. VLSI Design 2005, 165-170. Web SearchBibTeXDownload
2004
122Design of a nanosensor array architecture. Wei Xu, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. ACM Great Lakes Symposium on VLSI 2004, 298-303. Web SearchBibTeXDownload
121Reliability-Aware Co-Synthesis for Embedded Systems. Yuan Xie, Lin Li, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. ASAP 2004, 41-50. Web SearchBibTeXDownload
120Analyzing heap error behavior in embedded JVM environments. Guilin Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin. CODES+ISSS 2004, 230-235. Web SearchBibTeXDownload
119Scheduling Reusable Instructions for Power Reduction. Jie S. Hu, Narayanan Vijaykrishnan, Soontae Kim, Mahmut T. Kandemir, Mary Jane Irwin. DATE 2004, 148-155. Web SearchBibTeXDownload
118A Crosstalk Aware Interconnect with Variable Cycle Transmission. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. DATE 2004, 102-107. Web SearchBibTeXDownload
117Optimizing Leakage Energy Consumption in Cache Bitlines. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. Design Autom. for Emb. Sys. (9): 5-18 (2004). Web SearchBibTeXDownload
116Reducing leakage energy in FPGAs using region-constrained placement. Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan. FPGA 2004, 51-58. Web SearchBibTeXDownload
115A Dual-VDD Low Power FPGA Architecture. Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan. FPL 2004, 145-157. Web SearchBibTeXDownload
114Exploring Wakeup-Free Instruction Scheduling. Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin. HPCA 2004, 232-243. Web SearchBibTeXDownload
113Analyzing software influences on substrate noise: an ADC perspective. Frank Ghenassia, Narayanan Vijaykrishnan, Mary Jane Irwin. ICCAD 2004, 916-922. Web SearchBibTeXDownload
112Improving soft-error tolerance of FPGA configuration bits. Suresh Srinivasan, Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Yuan Xie, Mary Jane Irwin. ICCAD 2004, 107-110. Web SearchBibTeXDownload
111Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture. Wei-Lun Hung, Charles Addo-Quaye, Theo Theocharides, Yuan Xie, Narayanan Vijaykrishnan, Mary Jane Irwin. ICCD 2004, 430-437. Web SearchBibTeXDownload
110Search speed and power driven integrated software and hardware optimizations for motion estimation algorithms. Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan. ICME 2004, 707-710. Web SearchBibTeX
109A compiler-based approach for dynamically managing scratch-pad memories in embedded systems. Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh. IEEE Trans. on CAD of Integrated Circuits and Systems (23): 243-260 (2004). Web SearchBibTeXDownload
108Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices. Guangyu Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli. IEEE Trans. Parallel Distrib. Syst. (15): 795-809 (2004). Web SearchBibTeXDownload
107Characterization and modeling of run-time techniques for leakage power reduction. Yuh-Fang Tsai, D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. IEEE Trans. VLSI Syst. (12): 1221-1233 (2004). Web SearchBibTeXDownload
106Guest Editorial. Darrell Conklin, Tadeusz A. Wysocki, Hamid Sharif, L. C. Gundersen, P. P. Leahy, W. Hill, Jyh-Horng Wen, Shiuh-Jeng Wang, Yuh-Ren Tsai, Keh-Ming Lu. IEEE Trans. VLSI Syst. (12): 337-338 (2004). Cited by 2Web SearchBibTeX
105A Parallel Architecture for Secure FPGA Symmetric Encryption. Eric J. Swankoski, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. IPDPS 2004. Web SearchBibTeXDownload
104Improving Java Performance Using Dynamic Method Migration on FPGAs. Emanuele Lattanzi, Aman Gayasen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Luca Benini, Alessandro Bogliolo. IPDPS 2004. Web SearchBibTeXDownload
103Soft error and energy consumption interactions: a data cache perspective. Lin Li, Vijay Degalahal, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. ISLPED 2004, 132-137. Web SearchBibTeXDownload
102Field level analysis for heap space optimization in embedded java environments. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. ISMM 2004, 131-142. Web SearchBibTeXDownload
101The Effect of Threshold Voltages on the Soft Error Rate. Vijay Degalahal, R. Ramanarayanan, Narayanan Vijaykrishnan, Yuan Xie, Mary Jane Irwin. ISQED 2004, 503-508. Web SearchBibTeXDownload
100Evaluating Alternative Implementations for LDPC Decoder Check Node Function. Theo Theocharides, Greg M. Link, Eric J. Swankoski, Narayanan Vijaykrishnan, Mary Jane Irwin, Herman Schmit. ISVLSI 2004, 77-82. Web SearchBibTeXDownload
99Fault Tolerant Algorithms for Network-On-Chip Interconnect. Matthew Pirretti, Greg M. Link, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. ISVLSI 2004, 46-51. Web SearchBibTeXDownload
98Code protection for resource-constrained embedded devices. Hendra Saputra, Guangyu Chen, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. LCTES 2004, 240-248. Web SearchBibTeXDownload
97A generic reconfigurable neural network architecture as a network on chip. Theocharis Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Vamsi Srikantam. SoCC 2004, 191-194. Web SearchBibTeXDownload
96Power-efficient implementation of turbo decoder in SDR system. Byung-Tae Kang, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides. SoCC 2004, 119-122. Web SearchBibTeXDownload
95ChipPower: an architecture-level leakage simulator. Yuh-Fang Tsai, Ananth Hegde Ankadi, Narayanan Vijaykrishnan, Mary Jane Irwin, Theocharis Theocharides. SoCC 2004, 395-398. Web SearchBibTeXDownload
94Reducing instruction cache energy consumption using a compiler-based strategy. Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. TACO (1): 3-33 (2004). Web SearchBibTeXDownload
93Embedded Hardware Face Detection. Theo Theocharides, Greg M. Link, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf. VLSI Design 2004, 133. Web SearchBibTeXDownload
92Designing Leakage Aware Multipliers. M. DeRenzo, Mary Jane Irwin, Narayanan Vijaykrishnan. VLSI Design 2004, 654-657. Web SearchBibTeXDownload
91An Architecture for Motion Estimation in the Transform Domain. Jooheung Lee, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf. VLSI Design 2004, 1077-1082. Web SearchBibTeXDownload
90Instruction Scheduling for Low Power. Amisha Parikh, Soontae Kim, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. VLSI Signal Processing (37): 129-149 (2004). Web SearchBibTeXDownload
89Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues. J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, Soontae Kim. Wireless Networks (10): 183-195 (2004). Web SearchBibTeXDownload
2003
88Partitioned instruction cache architecture for energy efficiency. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin. ACM Trans. Embedded Comput. Syst. (2): 163-185 (2003). Web SearchBibTeXDownload
87Tracking object life cycle for leakage energy optimization. Guangyu Chen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mario Wolczko. CODES+ISSS 2003, 213-218. Web SearchBibTeXDownload
86VL-CDRAM: variable line sized cached DRAMs. Ananth Hegde, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. CODES+ISSS 2003, 132-137. Web SearchBibTeXDownload
85Implications of technology scaling on leakage reduction techniques. Yuh-Fang Tsai, David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. DAC 2003, 187-190. Web SearchBibTeXDownload
84Masking the Energy Behavior of DES Encryption. Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Richard R. Brooks, Soontae Kim, Wei Zhang. DATE 2003, 10084-10089. Web SearchBibTeXDownload
83Compiler Support for Reducing Leakage Energy Consumption. Wei Zhang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Vivek De. DATE 2003, 11146-11147. Web SearchBibTeXDownload
82CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Ismail Kadayif. DSD 2003, 41-49. Web SearchBibTeXDownload
81Adapative Error Protection for Energy Efficiency. Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. ICCAD 2003, 2-7. Web SearchBibTeXDownload
80Reducing dTLB Energy Through Dynamic Resizing. Victor Delaluz, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan. ICCD 2003, 358-363. Web SearchBibTeXDownload
79Computation and transmission energy modeling through profiling for MPEG4 video transmission. Amol Bhatkar, R. Chandramouli, Narayanan Vijaykrishnan, Mary Jane Irwin. ICME 2003, 281-284. Web SearchBibTeXDownload
78Leakage Current: Moore's Law Meets Static Power. Nam Sung Kim, Todd M. Austin, David Blaauw, Trevor N. Mudge, Krisztián Flautner, Jie S. Hu, Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan. IEEE Computer (36): 68-75 (2003). Web SearchBibTeXDownload
77Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte. IEEE Trans. Computers (52): 59-76 (2003). Web SearchBibTeXDownload
76Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices. Guilin Chen, Byung-Tae Kang, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Rajarathnam Chandramouli. IPDPS 2003, 34. Web SearchBibTeXDownload
75Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries. Sudhanva Gurumurthi, Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. IPDPS 2003, 33. Web SearchBibTeXDownload
74On load latency in low-power caches. Soontae Kim, Narayanan Vijaykrishnan, Mary Jane Irwin, Lizy Kurian John. ISLPED 2003, 258-261. Web SearchBibTeXDownload
73Energy optimization techniques in cluster interconnects. Eun Jung Kim, Ki Hwan Yum, Greg M. Link, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Mazin S. Yousif, Chita R. Das. ISLPED 2003, 459-464. Web SearchBibTeXDownload
72Exploiting program hotspots and code sequentiality for instruction cache leakage management. Jie S. Hu, A. Nadgir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir. ISLPED 2003, 402-407. Web SearchBibTeXDownload
71Estimating influence of data layout optimizations on SDRAM energy consumption. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Erik Brockmeyer, Francky Catthoor, Mary Jane Irwin. ISLPED 2003, 40-43. Web SearchBibTeXDownload
70Interplay of energy and performance for disk arrays running transaction processing workloads. Sudhanva Gurumurthi, Jianyong Zhang, Anand Sivasubramaniam, Mahmut T. Kandemir, Hubertus Franke, Narayanan Vijaykrishnan, Mary Jane Irwin. ISPASS 2003, 123-132. Web SearchBibTeXDownload
69Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch. Jie S. Hu, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir. ISVLSI 2003, 127-132. Web SearchBibTeXDownload
68Managing Leakage Energy in Cache Hierarchies. Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam. J. Instruction-Level Parallelism (5) (2003). Web SearchBibTeXDownload
67Adapting instruction level parallelism for optimizing leakage in VLIW architectures. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. LCTES 2003, 275-283. Web SearchBibTeXDownload
66The Sandbox Design Experience Course. Herman Schmit, Thomas Kroll, Max Khusid, Ivan S. Kourtev, Narayanan Vijaykrishnan, David L. Landis. MSE 2003, 39-40. Web SearchBibTeXDownload
65Heap compression for memory-constrained Java environments. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Bernd Mathiske, Mario Wolczko. OOPSLA 2003, 282-301. Web SearchBibTeXDownload
64Analyzing Soft Errors in Leakage Optimized SRAM Design. Vijay Degalahal, Narayanan Vijaykrishnan, Mary Jane Irwin. VLSI Design 2003, 227-233. Web SearchBibTeXDownload
63Energy Efficient and Reliable System Design. Narayanan Vijaykrishnan. VLSI-SOC 2003, 6-9. Web SearchBibTeX
2002
62Tuning garbage collection for reducing memory system energy in an embedded java environment. Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko. ACM Trans. Embedded Comput. Syst. (1): 27-55 (2002). Web SearchBibTeXDownload
61Understanding and improving operating system effects in control flow prediction. Tao Li, Lizy Kurian John, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Juan Rubio. ASPLOS 2002, 68-80. Web SearchBibTeXDownload
60Energy savings through compression in embedded Java environments. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf. CODES 2002, 163-168. Web SearchBibTeXDownload
59Scheduler-based DRAM energy management. Victor Delaluz, Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. DAC 2002, 697-702. Web SearchBibTeXDownload
58Power-Efficient Trace Caches. Jie S. Hu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. DATE 2002, 1091. Web SearchBibTeXDownload
57A Complete Phase-Locked Loop Power Consumption Model. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. DATE 2002, 1108. Web SearchBibTeXDownload
56EAC: A Compiler Framework for High-Level Energy Estimation and Optimization. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam. DATE 2002, 436-442. Web SearchBibTeXDownload
55Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach. Sudhanva Gurumurthi, Anand Sivasubramaniam, Mary Jane Irwin, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Tao Li, Lizy Kurian John. HPCA 2002, 141-150. Web SearchBibTeXDownload
54Tuning Garbage Collection in an Embedded Java Environment. Guangyu Chen, R. Shetty, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko. HPCA 2002, 92-103. Web SearchBibTeXDownload
53Power efficient adaptive M-QAM design using adaptive pipelined analog-to-digital converter. Byung-Tae Kang, Vijaykrishnan Narayanan, Mary Jane Irwin, Rajarathnam Chandramouli. ICASSP 2002, 2705-2708. Web SearchBibTeXDownload
52Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim, G. McFarland. ICCD 2002, 382-387. Web SearchBibTeXDownload
51Leakage Energy Management in Cache Hierarchies. Lin Li, Ismail Kadayif, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Anand Sivasubramaniam. IEEE PACT 2002, 131-140. Web SearchBibTeXDownload
50A clock power model to evaluate impact of architectural and technology optimizations. D. E. Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. IEEE Trans. VLSI Syst. (10): 844-855 (2002). Web SearchBibTeXDownload
49Designing Energy-Efficient Software. Anand Sivasubramaniam, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. IPDPS 2002. Web SearchBibTeXDownload
48Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. ISVLSI 2002, 20-25. Web SearchBibTeXDownload
47Impact of Technology Scaling in the Clock System Power. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin. ISVLSI 2002, 59-64. Web SearchBibTeXDownload
46Adaptive Garbage Collection for Battery-Operated Environments. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Mario Wolczko. Java Virtual Machine Research and Technology Symposium 2002, 1-12. Web SearchBibTeXDownload
45Using Memory Compression for Energy Reduction in an Embedded Java System. Guangyu Chen, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wayne Wolf. Journal of Circuits, Systems, and Computers (11): 537-556 (2002). Web SearchBibTeXDownload
44Compiler-directed cache polymorphism. Jie S. Hu, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hendra Saputra, Wei Zhang. LCTES-SCOPES 2002, 165-174. Web SearchBibTeXDownload
43Energy-conscious compilation based on voltage scaling. Hendra Saputra, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Jie S. Hu, Chung-Hsing Hsu, Ulrich Kremer. LCTES-SCOPES 2002, 2-11. Web SearchBibTeXDownload
42Compiler-directed instruction cache leakage optimization. Wei Zhang, Jie S. Hu, Vijay Degalahal, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. MICRO 2002, 208-218. Web SearchBibTeXDownload
41Energy-performance trade-offs for spatial access methods on memory-resident data. Ning An, Sudhanva Gurumurthi, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. VLDB J. (11): 179-197 (2002). Web SearchBibTeXDownload
40Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam, Ibrahim Kolcu. VLSI Design 2002, 288. Web SearchBibTeXDownload
39Evaluating Run-Time Techniques for Leakage Power Reduction. David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mary Jane Irwin. VLSI Design 2002, 31-38. Web SearchBibTeXDownload
2001
38Energy-efficient instruction cache using page-based placement. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. CASES 2001, 229-237. Web SearchBibTeXDownload
37Dynamic Management of Scratch-Pad Memory Space. Mahmut T. Kandemir, J. Ramanujam, Mary Jane Irwin, Narayanan Vijaykrishnan, Ismail Kadayif, Amisha Parikh. DAC 2001, 690-695. Web SearchBibTeXDownload
36DRAM Energy Management Using Software and Hardware Directed Power Mode Control. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin. HPCA 2001, 159-169. Web SearchBibTeXDownload
35Use of Local Memory for Efficient Java Execution. Samarjeet Singh Tomar, Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. ICCD 2001, 468-476. Web SearchBibTeX
34A Framework for Energy Estimation of VLIW Architecture. Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. ICCD 2001, 40-45. Web SearchBibTeX
33Java Runtime Systems: Characterization and Architectural Implications. Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam, Juan Rubio, Jyotsna Sabarinathan. IEEE Trans. Computers (50): 131-146 (2001). Web SearchBibTeXDownload
32Hardware and Software Techniques for Controlling DRAM Power Modes. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Mary Jane Irwin. IEEE Trans. Computers (50): 1154-1173 (2001). Web SearchBibTeXDownload
31Influence of compiler optimizations on system power. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye. IEEE Trans. VLSI Syst. (9): 801-804 (2001). Web SearchBibTeXDownload
30Design considerations for databus charge recovery. Benjamin Bishop, V. Lyuboslavsky, Narayanan Vijaykrishnan, Mary Jane Irwin. IEEE Trans. VLSI Syst. (9): 104-106 (2001). Cited by 4Web SearchBibTeXDownload
29Influence of Array Allocation Mechanisms on Memory System Energy. R. Athavale, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. IPDPS 2001, 3. Web SearchBibTeX
28Power-aware partitioned cache architectures. Soontae Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Anand Sivasubramaniam, Mary Jane Irwin, E. Geethanjali. ISLPED 2001, 64-67. Web SearchBibTeXDownload
27Energy Behavior of Java Applications from the Memory Perspective. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Soontae Kim, Samarjeet Singh Tomar, Anand Sivasubramaniam, Mary Jane Irwin. Java Virtual Machine Research and Technology Symposium 2001, 207-220. Web SearchBibTeXDownload
26Morphable Cache Architectures: Potential Benefits. Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, J. Ramanujam. LCTES/OM 2001, 128-137. Web SearchBibTeXDownload
25Exploiting VLIW schedule slacks for dynamic and leakage energy reduction. Wei Zhang, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, David Duarte, Yuh-Fang Tsai. MICRO 2001, 102-113. Web SearchBibTeXDownload
24SoC Design Skills: Collaboration Builds a Stronger SoC Design Team. Pradeep K. Khosla, Herman Schmit, Mary Jane Irwin, Narayanan Vijaykrishnan, Tom Cain, Steven P. Levitan, Dave Landis. MSE 2001, 42-43. Web SearchBibTeXDownload
23vEC: virtual energy counters. Ismail Kadayif, T. Chinoda, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Anand Sivasubramaniam. PASTE 2001, 28-31. Web SearchBibTeXDownload
22Analyzing energy behavior of spatial access methods for memory-resident data. Ning An, Anand Sivasubramaniam, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Sudhanva Gurumurthi. VLDB 2001, 411-420. Web SearchBibTeXDownload
21Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks. David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir. VLSI Design 2001, 248-253. Web SearchBibTeXDownload
2000
20A comparative study of power efficient SRAM designs. Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin. ACM Great Lakes Symposium on VLSI 2000, 117-122. Web SearchBibTeXDownload
19Energy-oriented compiler optimizations for partitioned memory architectures. Victor Delaluz, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. CASES 2000, 138-147. Web SearchBibTeXDownload
18Influence of compiler optimizations on system power. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Wu Ye. DAC 2000, 304-307. Web SearchBibTeXDownload
17The design and use of simplepower: a cycle-accurate energy estimation tool. Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. DAC 2000, 340-345. Web SearchBibTeXDownload
16Data Organization and Retrieval on Parallel Air Channels. J. Juran, Ali R. Hurson, Narayanan Vijaykrishnan, S. Boonsiriwattanakul. HiPC 2000, 501-510. Web SearchBibTeXDownload
15Energy-Aware Instruction Scheduling. Amisha Parikh, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin. HiPC 2000, 335-344. Web SearchBibTeXDownload
14Architectural Issues in Java Runtime Systems. Ramesh Radhakrishnan, Narayanan Vijaykrishnan, Lizy Kurian John, Anand Sivasubramaniam. HPCA 2000, 387-398. Web SearchBibTeXDownload
13Using complete system simulation to characterize SPECjvm98 benchmarks. Tao Li, Lizy Kurian John, Narayanan Vijaykrishnan, Anand Sivasubramaniam, Jyotsna Sabarinathan, Anupama Murthy. ICS 2000, 22-33. Web SearchBibTeXDownload
12Energy-driven integrated hardware-software optimizations using SimplePower. Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye. ISCA 2000, 95-106. Web SearchBibTeXDownload
11Memory system energy (poster session): influence of hardware-software optimizations. G. Esakkimuthu, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. ISLPED 2000, 244-246. Web SearchBibTeXDownload
10Experimental Evaluation of Energy Behavior of Iteration Space Tiling. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim. LCPC 2000, 142-157. Web SearchBibTeXDownload
9Towards Energy-Aware Iteration Space Tiling. Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin, Hyun Suk Kim. LCTES 2000, 211-215. Web SearchBibTeXDownload
8A Holistic Approach to System Level Energy Optimization. Mary Jane Irwin, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Anand Sivasubramaniam. PATMOS 2000, 88-107. Web SearchBibTeXDownload
1999
7Tuning Branch Predictors to Support Virtual Method Invocation in Java. Narayanan Vijaykrishnan, N. Ranganathan. COOTS 1999, 217-228. Web SearchBibTeXDownload
6Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan. VLSI Design 1999, 440. Web SearchBibTeXDownload
1998
5Object-Oriented Architectural Support for a Java Processor. Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla. ECOOP 1998, 330-354. Web SearchBibTeXDownload
4A linear array processor with dynamic frequency clocking for image processing applications. Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar. IEEE Trans. Circuits Syst. Video Techn. (8): 435-445 (1998). Web SearchBibTeXDownload
1996
3A VLSI array architecture with dynamic frequency clocking. N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar. ICCD 1996, 137-140. Web SearchBibTeXDownload
2DFLAP: a dynamic frequency linear array processor. Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar. ICIP (2) 1996, 1007-1010. Web SearchBibTeXDownload
1SUBGEN: a genetic approach for subcircuit extraction. Narayanan Vijaykrishnan, N. Ranganathan. VLSI Design 1996, 343-345. Web SearchBibTeXDownload
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