| 2010 |
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| 25 | Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture. Wei Zhang, Niraj K. Jha, Li Shang. JETC (6) (2010). Web SearchBibTeXDownload |
| 2009 |
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| 24 | A hybrid nano/CMOS dynamically reconfigurable system - Part I: Architecture. Wei Zhang, Niraj K. Jha, Li Shang. JETC (5) (2009). Web SearchBibTeXDownload |
| 23 | Design space exploration and data memory architecture design for a hybrid nano/CMOS dynamically reconfigurable architecture. Wei Zhang, Niraj K. Jha, Li Shang. JETC (5) (2009). Web SearchBibTeXDownload |
| 22 | A hybrid Nano/CMOS dynamically reconfigurable system - Part II: Design optimization flow. Wei Zhang, Niraj K. Jha, Li Shang. JETC (5) (2009). Web SearchBibTeXDownload |
| 2008 |
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| 21 | Toward Ideal On-Chip Communication Using Express Virtual Channels. Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha. IEEE Micro (28): 80-90 (2008). Web SearchBibTeXDownload |
| 20 | System-Level Dynamic Thermal Management for High-Performance Microprocessors. Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha. IEEE Trans. on CAD of Integrated Circuits and Systems (27): 96-108 (2008). Web SearchBibTeXDownload |
| 19 | Automatic Test Generation for Combinational Threshold Logic Networks. Pallav Gupta, Rui Zhang, Niraj K. Jha. IEEE Trans. VLSI Syst. (16): 1035-1045 (2008). Web SearchBibTeXDownload |
| 18 | A system-level perspective for efficient NoC design. Amit Kumar, Niket Agarwal, Li-Shiuan Peh, Niraj K. Jha. IPDPS 2008, 1-5. Web SearchBibTeXDownload |
| 17 | Token flow control. Amit Kumar, Li-Shiuan Peh, Niraj K. Jha. MICRO 2008, 342-353. Web SearchBibTeXDownload |
| 2007 |
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| 16 | NanoMap: An Integrated Design Optimization Flow for a Hybrid Nanotube/CMOS Dynamically Reconfigurable Architecture. Wei Zhang, Li Shang, Niraj K. Jha. DAC 2007, 300-305. Web SearchBibTeXDownload |
| 15 | A 4.6Tbits/s 3.6GHz single-cycle NoC router with a novel switch allocator in 65nm CMOS. Amit Kumar, Partha Kundu, Arvind P. Singh, Li-Shiuan Peh, Niraj K. Jha. ICCD 2007, 63-70. Web SearchBibTeXDownload |
| 14 | Majority and Minority Network Synthesis With Application to QCA-, SET-, and TPL-Based Nanotechnologies. Rui Zhang, Pallav Gupta, Niraj K. Jha. IEEE Trans. on CAD of Integrated Circuits and Systems (26): 1233-1245 (2007). Cited by 3Web SearchBibTeXDownload |
| 13 | Express virtual channels: towards the ideal interconnection fabric. Amit Kumar, Li-Shiuan Peh, Partha Kundu, Niraj K. Jha. ISCA 2007, 150-161. Web SearchBibTeXDownload |
| 2006 |
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| 12 | Threshold/majority logic synthesis and concurrent error detection targeting nanoelectronic implementations. Rui Zhang, Niraj K. Jha. ACM Great Lakes Symposium on VLSI 2006, 8-13. Cited by 4Web SearchBibTeXDownload |
| 11 | NATURE: a hybrid nanotube/CMOS dynamically reconfigurable architecture. Wei Zhang, Niraj K. Jha, Li Shang. DAC 2006, 711-716. Web SearchBibTeXDownload |
| 10 | HybDTM: a coordinated hardware-software approach for dynamic thermal management. Amit Kumar, Li Shang, Li-Shiuan Peh, Niraj K. Jha. DAC 2006, 548-553. Web SearchBibTeXDownload |
| 9 | Temperature-Aware On-Chip Networks. Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha. IEEE Micro (26): 130-139 (2006). Web SearchBibTeXDownload |
| 8 | State Encoding of Finite-State Machines Targeting Threshold and Majority Logic Based Implementations with Application to Nanotechnologies. Rui Zhang, Niraj K. Jha. VLSI Design 2006, 317-322. Web SearchBibTeXDownload |
| 2005 |
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| 7 | ALLCN: An Automatic Logic-to-Layout Tool for Carbon Nanotube Based Nanotechnology. Wei Zhang, Niraj K. Jha. ICCD 2005, 281-288. Web SearchBibTeXDownload |
| 6 | Threshold network synthesis and optimization and its application to nanotechnologies. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha. IEEE Trans. on CAD of Integrated Circuits and Systems (24): 107-118 (2005). Cited by 35Web SearchBibTeXDownload |
| 5 | Synthesis of Majority and Minority Networks and Its Applications to QCA, TPL and SET Based Nanotechnologies. Rui Zhang, Pallav Gupta, Niraj K. Jha. VLSI Design 2005, 229-234. Cited by 20Web SearchBibTeXDownload |
| 2004 |
|---|
| 4 | Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies. Rui Zhang, Pallav Gupta, Lin Zhong, Niraj K. Jha. DATE 2004, 904-909. Cited by 15Web SearchBibTeXDownload |
| 3 | An Automatic Test Pattern Generation Framework for Combinational Threshold Logic Networks. Pallav Gupta, Rui Zhang, Niraj K. Jha. ICCD 2004, 540-543. Cited by 8Web SearchBibTeXDownload |
| 2 | Thermal Modeling, Characterization and Management of On-Chip Networks. Li Shang, Li-Shiuan Peh, Amit Kumar, Niraj K. Jha. MICRO 2004, 67-78. Web SearchBibTeXDownload |
| 1998 |
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| 1 | Guest Editorial. Darrell Conklin, Tadeusz A. Wysocki, Hamid Sharif, L. C. Gundersen, P. P. Leahy, W. Hill, Jyh-Horng Wen, Shiuh-Jeng Wang, Yuh-Ren Tsai, Keh-Ming Lu. J. Electronic Testing (13): 77 (1998). Cited by 2Web SearchBibTeXDownload |
