Onur Mutlu

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2011
48Aérgia: A Network-on-Chip Exploiting Packet Latency Slack. Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das. IEEE Micro (31): 29-41 (2011). Web SearchBibTeXDownload
47Data Marshaling for Multicore Systems. M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt. IEEE Micro (31): 56-64 (2011). Web SearchBibTeXDownload
46Top Picks [Guest editors' introduction]. Yale N. Patt, Onur Mutlu. IEEE Micro (31): 6-10 (2011). Web SearchBibTeXDownload
45Thread Cluster Memory Scheduling. Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter. IEEE Micro (31): 78-89 (2011). Web SearchBibTeXDownload
44Prefetch-Aware Memory Controllers. Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt. IEEE Trans. Computers (60): 1406-1430 (2011). Web SearchBibTeXDownload
43Prefetch-aware shared resource management for multi-core systems. Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt. ISCA 2011, 141-152. Web SearchBibTeXDownload
2010
42Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems. Eiman Ebrahimi, Chang Joo Lee, Onur Mutlu, Yale N. Patt. ASPLOS 2010, 335-346. Web SearchBibTeXDownload
41ATLAS: A scalable and high-performance scheduling algorithm for multiple memory controllers. Yoongu Kim, Dongsu Han, Onur Mutlu, Mor Harchol-Balter. HPCA 2010, 1-12. Web SearchBibTeXDownload
40Accelerating Critical Section Execution with Asymmetric Multicore Architectures. M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt. IEEE Micro (30): 60-70 (2010). Web SearchBibTeXDownload
39Phase-Change Technology and the Future of Main Memory. Benjamin C. Lee, Ping Zhou, Jun Yang, Youtao Zhang, Bo Zhao, Engin Ipek, Onur Mutlu, Doug Burger. IEEE Micro (30): 143 (2010). Web SearchBibTeXDownload
38Data marshaling for multi-core architectures. M. Aater Suleman, Onur Mutlu, José A. Joao, Khubaib, Yale N. Patt. ISCA 2010, 441-450. Web SearchBibTeXDownload
37Aérgia: exploiting packet latency slack in on-chip networks. Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das. ISCA 2010, 106-116. Web SearchBibTeXDownload
36Thread Cluster Memory Scheduling: Exploiting Differences in Memory Access Behavior. Yoongu Kim, Michael Papamichael, Onur Mutlu, Mor Harchol-Balter. MICRO 2010, 65-76. Web SearchBibTeXDownload
2009
35Accelerating critical section execution with asymmetric multi-core architectures. M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt. ASPLOS 2009, 253-264. Web SearchBibTeXDownload
34Techniques for bandwidth-efficient prefetching of linked data structures in hybrid prefetching systems. Eiman Ebrahimi, Onur Mutlu, Yale N. Patt. HPCA 2009, 7-17. Web SearchBibTeXDownload
33Virtual Program Counter (VPC) Prediction: Very Low Cost Indirect Branch Prediction Using Conditional Branch Prediction Hardware. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn. IEEE Trans. Computers (58): 1153-1170 (2009). Web SearchBibTeXDownload
32Flexible reference-counting-based hardware acceleration for garbage collection. José A. Joao, Onur Mutlu, Yale N. Patt. ISCA 2009, 418-428. Web SearchBibTeXDownload
31Coordinated control of multiple prefetchers in multi-core systems. Eiman Ebrahimi, Onur Mutlu, Chang Joo Lee, Yale N. Patt. MICRO 2009, 316-326. Web SearchBibTeXDownload
30Application-aware prioritization mechanisms for on-chip networks. Reetuparna Das, Onur Mutlu, Thomas Moscibroda, Chita R. Das. MICRO 2009, 280-291. Web SearchBibTeXDownload
29Improving memory bank-level parallelism in the presence of prefetching. Chang Joo Lee, Veynu Narasiman, Onur Mutlu, Yale N. Patt. MICRO 2009, 327-336. Web SearchBibTeXDownload
2008
28Improving the performance of object-oriented languages with dynamic predication of indirect jumps. José A. Joao, Onur Mutlu, Hyesoon Kim, Rishi Agarwal, Yale N. Patt. ASPLOS 2008, 80-90. Web SearchBibTeXDownload
27Performance-aware speculation control using wrong path usefulness prediction. Chang Joo Lee, Hyesoon Kim, Onur Mutlu, Yale N. Patt. HPCA 2008, 39-49. Web SearchBibTeXDownload
26Guest Editors' Introduction: Interaction of Many-Core Computer Architecture and Operating Systems. Sangyeun Cho, Tao Li, Onur Mutlu. IEEE Micro (28): 2-5 (2008). Web SearchBibTeXDownload
25Self-Optimizing Memory Controllers: A Reinforcement Learning Approach. Engin Ipek, Onur Mutlu, José F. Martínez, Rich Caruana. ISCA 2008, 39-50. Web SearchBibTeXDownload
24Prefetch-Aware DRAM Controllers. Chang Joo Lee, Onur Mutlu, Veynu Narasiman, Yale N. Patt. MICRO 2008, 200-209. Web SearchBibTeXDownload
2007
23Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt. CGO 2007, 367-378. Web SearchBibTeXDownload
22Dynamic Predication of Indirect Jumps. José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt. Computer Architecture Letters (7): 1-4 (2007). Web SearchBibTeXDownload
21Feedback Directed Prefetching: Improving the Performance and Bandwidth-Efficiency of Hardware Prefetchers. Santhosh Srinath, Onur Mutlu, Hyesoon Kim, Yale N. Patt. HPCA 2007, 63-74. Web SearchBibTeXDownload
20Diverge-Merge Processor: Generalized and Energy-Efficient Dynamic Predication. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt. IEEE Micro (27): 94-104 (2007). Web SearchBibTeXDownload
19VPC prediction: reducing the cost of indirect branches via hardware-based dynamic devirtualization. Hyesoon Kim, José A. Joao, Onur Mutlu, Chang Joo Lee, Yale N. Patt, Robert Cohn. ISCA 2007, 424-435. Web SearchBibTeXDownload
2006
182D-Profiling: Detecting Input-Dependent Branches with a Single Input Data Set. Hyesoon Kim, M. Aater Suleman, Onur Mutlu, Yale N. Patt. CGO 2006, 159-172. Web SearchBibTeXDownload
17Wish Branches: Enabling Adaptive and Aggressive Predicated Execution. Hyesoon Kim, Onur Mutlu, Yale N. Patt, Jared Stark. IEEE Micro (26): 48-58 (2006). Web SearchBibTeXDownload
16Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance. Onur Mutlu, Hyesoon Kim, Yale N. Patt. IEEE Micro (26): 10-20 (2006). Web SearchBibTeXDownload
15Address-Value Delta (AVD) Prediction: A Hardware Technique for Efficiently Parallelizing Dependent Cache Misses. Onur Mutlu, Hyesoon Kim, Yale N. Patt. IEEE Trans. Computers (55): 1491-1508 (2006). Web SearchBibTeXDownload
14A Case for MLP-Aware Cache Replacement. Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt. ISCA 2006, 167-178. Web SearchBibTeXDownload
13Diverge-Merge Processor (DMP): Dynamic Predicated Execution of Complex Control-Flow Graphs Based on Frequently Executed Paths. Hyesoon Kim, José A. Joao, Onur Mutlu, Yale N. Patt. MICRO 2006, 53-64. Web SearchBibTeXDownload
2005
12On Reusing the Results of Pre-Executed Instructions in a Runahead Execution Processor. Onur Mutlu, Hyesoon Kim, Jared Stark, Yale N. Patt. Computer Architecture Letters (4): 2 (2005). Web SearchBibTeXDownload
11Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt. DSN 2005, 434-443. Web SearchBibTeXDownload
10An Analysis of the Performance Impact of Wrong-Path Memory References on Out-of-Order and Runahead Execution Processors. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt. IEEE Trans. Computers (54): 1556-1571 (2005). Web SearchBibTeXDownload
9Using the First-Level Caches as Filters to Reduce the Pollution Caused by Speculative Memory References. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt. International Journal of Parallel Programming (33): 529-559 (2005). Web SearchBibTeXDownload
8Techniques for Efficient Processing in Runahead Execution Engines. Onur Mutlu, Hyesoon Kim, Yale N. Patt. ISCA 2005, 370-381. Web SearchBibTeXDownload
7Address-Value Delta (AVD) Prediction: Increasing the Effectiveness of Runahead Execution by Exploiting Regular Memory Allocation Patterns. Onur Mutlu, Hyesoon Kim, Yale N. Patt. MICRO 2005, 233-244. Web SearchBibTeXDownload
6Wish Branches: Combining Conditional Branching and Predication for Adaptive Predicated Execution. Hyesoon Kim, Onur Mutlu, Jared Stark, Yale N. Patt. MICRO 2005, 43-54. Web SearchBibTeXDownload
2004
5Wrong Path Events: Exploiting Unusual and Illegal Program Behavior for Early Misprediction Detection and Recovery. David N. Armstrong, Hyesoon Kim, Onur Mutlu, Yale N. Patt. MICRO 2004, 119-128. Web SearchBibTeXDownload
4Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt. SBAC-PAD 2004, 2-9. Web SearchBibTeXDownload
3Understanding the effects of wrong-path memory references on processor performance. Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale N. Patt. WMPI 2004, 56-64. Web SearchBibTeXDownload
2003
2Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt. HPCA 2003, 129-140. Web SearchBibTeXDownload
1Runahead Execution: An Effective Alternative to Large Instruction Windows. Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt. IEEE Micro (23): 20-25 (2003). Web SearchBibTeXDownload
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