| 2012 |
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| 12 | Power-Scalable, Complex Bandpass/Low-Pass Filter With I/Q Imbalance Calibration for a Multimode GNSS Receiver. Yang Xu, Baoyong Chi, Xiaobao Yu, Nan Qi, Patrick Chiang, Zhihua Wang. IEEE Trans. on Circuits and Systems (59-II): 30-34 (2012). Web SearchBibTeXDownload |
| 2011 |
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| 11 | Low-power 8Gb/s near-threshold serial link receivers using super-harmonic injection locking in 65nm CMOS. Kangmin Hu, Tao Jiang, Sam Palermo, Patrick Yin Chiang. CICC 2011, 1-4. Web SearchBibTeXDownload |
| 2010 |
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| 10 | Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS. Tao Jiang, Wing Liu, Freeman Y. Zhong, Charlie Zhong, Patrick Yin Chiang. CICC 2010, 1-4. Web SearchBibTeXDownload |
| 9 | Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges. Patrick Yin Chiang, Sirikarn Woracheewan, Changhui Hu, Lei Guo, Rahul Khanna, Jay J. Nejedlo, Huaping Liu. IEEE Design & Test of Computers (27): 32-43 (2010). Web SearchBibTeXDownload |
| 8 | A 0.6 mW/Gb/s, 6.4-7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS. Kangmin Hu, Tao Jiang, Jingguang Wang, Frank O'Mahony, Patrick Yin Chiang. J. Solid-State Circuits (45): 899-908 (2010). Web SearchBibTeXDownload |
| 2009 |
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| 7 | Express Virtual Channels with Capacitively Driven Global Links. Tushar Krishna, Amit Kumar, Li-Shiuan Peh, Jacob Postman, Patrick Chiang, Mattan Erez. IEEE Micro (29): 48-61 (2009). Web SearchBibTeXDownload |
| 6 | Sense Amplifier Power and Delay Characterization for Operation under Low-Vdd and Low-voltage Clock Swing. Tao Jiang, Patrick Yin Chiang. ISCAS 2009, 181-184. Web SearchBibTeXDownload |
| 5 | Comparison of On-die Global Clock Distribution Methods for Parallel Serial Links. Kangmin Hu, Tao Jiang, Patrick Chiang. ISCAS 2009, 1843-1846. Web SearchBibTeXDownload |
| 4 | A 10Gb/s Wire-line Transceiver with Half Rate Period Calibration CDR. Zhuo Gao, Hang Yu, Patrick Chiang, Yi Yang, Feng Zhang. ISCAS 2009, 1827-1830. Web SearchBibTeXDownload |
| 2008 |
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| 3 | NoC with Near-Ideal Express Virtual Channels Using Global-Line Communication. Tushar Krishna, Amit Kumar, Patrick Chiang, Mattan Erez, Li-Shiuan Peh. Hot Interconnects 2008, 11-20. Web SearchBibTeXDownload |
| 2007 |
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| 2 | Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable Capacitance. Yike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang, Yongming Li, Zhihua Wang, Patrick Chiang. ISCAS 2007, 2562-2565. Web SearchBibTeXDownload |
| 2001 |
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| 1 | Monolithic chaotic communications system. P. Chiang, William J. Dally, E. Lee. ISCAS (3) 2001, 325-328. Web SearchBibTeXDownload |
