| 2011 |
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| 8 | ACCESS: Smart scheduling for asymmetric cache CMPs. Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das. HPCA 2011, 527-538. Web SearchBibTeXDownload |
| 7 | CHOP: Integrating DRAM Caches for CMP Server Platforms. Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian. IEEE Micro (31): 99-108 (2011). Web SearchBibTeXDownload |
| 2010 |
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| 6 | CHOP: Adaptive filter-based DRAM caching for CMP server platforms. Xiaowei Jiang, Niti Madan, Li Zhao, Mike Upton, Ravishankar Iyer, Srihari Makineni, Donald Newell, Yan Solihin, Rajeev Balasubramonian. HPCA 2010, 1-12. Web SearchBibTeXDownload |
| 5 | Quality of service shared cache management in chip multiprocessor architecture. Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer. TACO (7): 14 (2010). Web SearchBibTeXDownload |
| 2009 |
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| 4 | A case for dynamic frequency tuning in on-chip networks. Asit K. Mishra, Reetuparna Das, Soumya Eachempati, Ravishankar Iyer, Narayanan Vijaykrishnan, Chita R. Das. MICRO 2009, 292-303. Web SearchBibTeXDownload |
| 3 | Architecture Support for Improving Bulk Memory Copying and Initialization Performance. Xiaowei Jiang, Yan Solihin, Li Zhao, Ravishankar Iyer. PACT 2009, 169-180. Web SearchBibTeXDownload |
| 2008 |
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| 2 | Performance and power optimization through data compression in Network-on-Chip architectures. Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Ravishankar Iyer, Mazin S. Yousif, Chita R. Das. HPCA 2008, 215-225. Web SearchBibTeXDownload |
| 2007 |
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| 1 | A Framework for Providing Quality of Service in Chip Multi-Processors. Fei Guo, Yan Solihin, Li Zhao, Ravishankar Iyer. MICRO 2007, 343-355. Web SearchBibTeXDownload |
