| 2011 |
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| 15 | Full-chip runtime error-tolerant thermal estimation and prediction for practical thermal management. Hai Wang, Sheldon X.-D. Tan, Guangdeng Liao, Rafael Quintanilla, Ashish Gupta. ICCAD 2011, 716-723. Web SearchBibTeXDownload |
| 2008 |
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| 14 | FEKIS: a fast architecture-level thermal analyzer for online thermal regulation. Pu Liu, Sheldon X.-D. Tan, Wei Wu, Murli Tirumala. ACM Great Lakes Symposium on VLSI 2008, 411-416. Web SearchBibTeXDownload |
| 13 | DeMOR: decentralized model order reduction of linear networks with massive ports. Boyuan Yan, Lingfei Zhou, Sheldon X.-D. Tan, Jie Chen, Bruce McGaughy. DAC 2008, 409-414. Web SearchBibTeXDownload |
| 12 | A Fast Architecture-Level Thermal Analysis Method for Runtime Thermal Regulation. Sheldon X.-D. Tan, Pu Liu, Lin Jiang, Wei Wu, Murli Tirumala. J. Low Power Electronics (4): 139-148 (2008). Web SearchBibTeXDownload |
| 2007 |
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| 11 | Efficient power modeling and software thermal sensing for runtime temperature monitoring. Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan. ACM Trans. Design Autom. Electr. Syst. (12) (2007). Web SearchBibTeXDownload |
| 10 | Improving the reliability of on-chip data caches under process variations. Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu. ICCD 2007, 325-332. Web SearchBibTeXDownload |
| 2006 |
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| 9 | A systematic method for functional unit power estimation in microprocessors. Wei Wu, Lingling Jin, Jun Yang, Pu Liu, Sheldon X.-D. Tan. DAC 2006, 554-557. Cited by 15Web SearchBibTeXDownload |
| 8 | Fast Thermal Simulation for Runtime Temperature Tracking and Management. Pu Liu, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang. IEEE Trans. on CAD of Integrated Circuits and Systems (25): 2882-2893 (2006). Web SearchBibTeXDownload |
| 7 | Partitioning-Based Approach to Fast On-Chip Decoupling Capacitor Budgeting and Minimization. Hang Li, Jeffrey Fan, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong. IEEE Trans. on CAD of Integrated Circuits and Systems (25): 2402-2412 (2006). Web SearchBibTeXDownload |
| 2005 |
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| 6 | Partitioning-based approach to fast on-chip decap budgeting and minimization. Hang Li, Zhenyu Qi, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong. DAC 2005, 170-175. Web SearchBibTeXDownload |
| 5 | Fast thermal simulation for architecture level dynamic thermal management. Pu Liu, Zhenyu Qi, Hang Li, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang. ICCAD 2005, 639-644. Cited by 17Web SearchBibTeX |
| 4 | An efficient method for terminal reduction of interconnect circuits considering delay variations. Pu Liu, Sheldon X.-D. Tan, Hang Li, Zhenyu Qi, Jun Kong, Bruce McGaughy, Lei He. ICCAD 2005, 821-826. Web SearchBibTeX |
| 3 | Efficient Thermal Simulation for Run-Time Temperature Tracking and Management. Hang Li, Pu Liu, Zhenyu Qi, Lingling Jin, Wei Wu, Sheldon X.-D. Tan, Jun Yang. ICCD 2005, 130-136. Web SearchBibTeXDownload |
| 2 | Fast Decap Allocation Algorithm For Robust On-Chip Power Delivery. Zhenyu Qi, Hang Li, Sheldon X.-D. Tan, Lifeng Wu, Yici Cai, Xianlong Hong. ISQED 2005, 542-547. Web SearchBibTeXDownload |
| 2004 |
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| 1 | Hierarchical Modeling and Simulation of Large Analog Circuits. Sheldon X.-D. Tan, Zhenyu Qi, Hang Li. DATE 2004, 740-741. Web SearchBibTeXDownload |
