| 2011 |
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| 9 | Adaptive Cache Design to Enable Reliable Low-Voltage Operation. Alaa R. Alameldeen, Zeshan Chishti, Chris Wilkerson, Wei Wu, Shih-Lien Lu. IEEE Trans. Computers (60): 50-63 (2011). Web SearchBibTeXDownload |
| 8 | Energy-efficient cache design using variable-strength error-correcting codes. Alaa R. Alameldeen, Ilya Wagner, Zeshan Chishti, Wei Wu, Chris Wilkerson, Shih-Lien Lu. ISCA 2011, 461-472. Web SearchBibTeXDownload |
| 2010 |
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| 7 | Reducing cache power with low-cost, multi-bit error-correcting codes. Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, Shih-Lien Lu. ISCA 2010, 83-93. Web SearchBibTeXDownload |
| 2009 |
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| 6 | Trading Off Cache Capacity for Low-Voltage Operation. Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu. IEEE Micro (29): 96-103 (2009). Web SearchBibTeXDownload |
| 5 | Low power adaptive pipeline based on instruction isolation. Seung Eun Lee, Chris Wilkerson, Ming Zhang, Rajendra Yavatkar, Shih-Lien Lu, Nader Bagherzadeh. ISQED 2009, 788-793. Web SearchBibTeXDownload |
| 4 | Improving cache lifetime reliability at ultra-low voltages. Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerson, Wei Wu, Shih-Lien Lu. MICRO 2009, 89-99. Web SearchBibTeXDownload |
| 2008 |
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| 3 | Trading off Cache Capacity for Reliability to Enable Low Voltage Operation. Chris Wilkerson, Hongliang Gao, Alaa R. Alameldeen, Zeshan Chishti, Muhammad M. Khellah, Shih-Lien Lu. ISCA 2008, 203-214. Web SearchBibTeXDownload |
| 2007 |
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| 2 | Improving the reliability of on-chip data caches under process variations. Wei Wu, Sheldon X.-D. Tan, Jun Yang, Shih-Lien Lu. ICCD 2007, 325-332. Web SearchBibTeXDownload |
| 1 | RAMP: Research Accelerator for Multiple Processors. John Wawrzynek, David A. Patterson, Mark Oskin, Shih-Lien Lu, Christoforos E. Kozyrakis, James C. Hoe, Derek Chiou, Krste Asanovic. IEEE Micro (27): 46-57 (2007). Web SearchBibTeXDownload |
