| 2011 |
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| 18 | Modelling circuit performance variations due to statistical variability: Monte Carlo static timing analysis. Michael Merrett, P. Asenov, Yangang Wang, Mark Zwolinski, Dave Reid, Campbell Millar, Scott Roy, Zhenyu Liu, Stephen B. Furber, Asen Asenov. DATE 2011, 1537-1540. Web SearchBibTeXDownload |
| 2010 |
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| 17 | Modeling Spiking Neural Networks on SpiNNaker. Xin Jin, Mikel Luján, Luis A. Plana, Sergio Davies, Steve Temple, Steve Furber. Computing in Science and Engineering (12): 91-97 (2010). Web SearchBibTeXDownload |
| 16 | A Multicast Routing Scheme for a Universal Spiking Neural Network Architecture. Jian Wu, Steve Furber. Comput. J. (53): 280-288 (2010). Web SearchBibTeXDownload |
| 15 | Efficient parallel implementation of multilayer backpropagation networks on SpiNNaker. Xin Jin, Mikel Luján, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Steve Furber. Conf. Computing Frontiers 2010, 89-90. Web SearchBibTeXDownload |
| 14 | Scalable event-driven native parallel processing: the SpiNNaker neuromimetic system. Alexander D. Rast, Xin Jin, Francesco Galluppi, Luis A. Plana, Cameron Patterson, Stephen B. Furber. Conf. Computing Frontiers 2010, 21-30. Web SearchBibTeXDownload |
| 13 | Implementing spike-timing-dependent plasticity on SpiNNaker neuromorphic hardware. Xin Jin, Alexander D. Rast, Francesco Galluppi, Sergio Davies, Steve Furber. IJCNN 2010, 1-8. Web SearchBibTeXDownload |
| 12 | Algorithm and software for simulation of spiking neural networks on the multi-chip SpiNNaker system. Xin Jin, Francesco Galluppi, Cameron Patterson, Alexander D. Rast, Sergio Davies, Steve Temple, Steve Furber. IJCNN 2010, 1-8. Web SearchBibTeXDownload |
| 11 | The Leaky Integrate-and-Fire neuron: A platform for synaptic model exploration on the SpiNNaker chip. Alexander D. Rast, Francesco Galluppi, Xin Jin, Steve Furber. IJCNN 2010, 1-8. Web SearchBibTeXDownload |
| 10 | Algorithm for Mapping Multilayer BP Networks onto the SpiNNaker Neuromorphic Hardware. Xin Jin, Mikel Luján, Muhammad Mukaram Khan, Luis A. Plana, Alexander D. Rast, Stephen R. Welbourne, Stephen B. Furber. ISPDC 2010, 9-16. Web SearchBibTeXDownload |
| 2009 |
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| 9 | Implementing Learning on the SpiNNaker Universal Neural Chip Multiprocessor. Xin Jin, Alexander D. Rast, Francesco Galluppi, Muhammad Mukaram Khan, Steve Furber. ICONIP (1) 2009, 425-432. Web SearchBibTeXDownload |
| 8 | Optimal connectivity in hardware-targetted MLP networks. Alexander D. Rast, Stephen R. Welbourne, Xin Jin, Steven B. Furber. IJCNN 2009, 2619-2626. Web SearchBibTeXDownload |
| 7 | A universal abstract-time platform for real-time neural networks. Alexander D. Rast, Mukaram M. Khan, Xin Jin, Luis A. Plana, Steven B. Furber. IJCNN 2009, 2611-2618. Web SearchBibTeXDownload |
| 6 | Event-Driven Configuration of a Neural Network CMP System over a Homogeneous Interconnect Fabric. Muhammad Mukaram Khan, Javier Navaridas, Alexander D. Rast, Xin Jin, Luis A. Plana, Mikel Luján, John V. Woods, José Miguel-Alonso, Steven B. Furber. ISPDC 2009, 54-61. Web SearchBibTeXDownload |
| 2008 |
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| 5 | The Deferred Event Model for Hardware-Oriented Spiking Neural Networks. Alexander D. Rast, Xin Jin, Mukaram Khan, Steve Furber. ICONIP (2) 2008, 1057-1064. Web SearchBibTeXDownload |
| 4 | SpiNNaker: Mapping neural networks onto a massively-parallel chip multiprocessor. Muhammad Mukaram Khan, David R. Lester, Luis A. Plana, Alexander D. Rast, Xin Jin, E. Painkras, Stephen B. Furber. IJCNN 2008, 2849-2856. Web SearchBibTeXDownload |
| 3 | Efficient modelling of spiking neural networks on a scalable chip multiprocessor. Xin Jin, Stephen B. Furber, John V. Woods. IJCNN 2008, 2812-2819. Web SearchBibTeXDownload |
| 2 | An On-Chip and Inter-Chip Communications Network for the SpiNNaker Massively-Parallel Neural Net Simulator. Luis A. Plana, John Bainbridge, Steve Furber, Sean Salisbury, Yebin Shi, Jian Wu. NOCS 2008, 215-216. Web SearchBibTeXDownload |
| 2007 |
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| 1 | A GALS Infrastructure for a Massively Parallel Multiprocessor. Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang. IEEE Design & Test of Computers (24): 454-463 (2007). Web SearchBibTeXDownload |
