Walid A. Najjar

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2011
96Massively parallel XML twig filtering using dynamic programming on FPGAs. Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras. ICDE 2011, 948-959. Web SearchBibTeXDownload
2010
95Designing Modular Hardware Accelerators in C with ROCCC 2.0. Jason R. Villarreal, Adrian Park, Walid A. Najjar, Robert Halstead. FCCM 2010, 127-134. Web SearchBibTeXDownload
94Accelerating XML Query Matching through Custom Stack Generation on FPGAs. Roger Moussalli, Mariam Salloum, Walid A. Najjar, Vassilis J. Tsotras. HiPEAC 2010, 141-155. Web SearchBibTeXDownload
93Accelerating Dynamic Time Warping Subsequence Search with GPUs and FPGAs. Doruk Sart, Abdullah Mueen, Walid A. Najjar, Eamonn J. Keogh, Vit Niennattrakul. ICDM 2010, 1001-1006. Web SearchBibTeXDownload
92Impact of high-level transformations within the ROCCC framework. Betul Buyukkurt, John Cortes, Jason R. Villarreal, Walid A. Najjar. TACO (7): 17 (2010). Web SearchBibTeXDownload
2009
91Energy-efficient encoding techniques for off-chip data buses. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar. ACM Trans. Embedded Comput. Syst. (8) (2009). Web SearchBibTeXDownload
90Boosting XML filtering through a scalable FPGA-based architecture. Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Vassilis J. Tsotras, Walid A. Najjar. CIDR 2009. Web SearchBibTeXDownload
89Boosting XML Filtering with a Scalable FPGA-based Architecture. Abhishek Mitra, Marcos R. Vieira, Petko Bakalov, Walid A. Najjar, Vassilis J. Tsotras. CoRR (abs/0909.1781) (2009). Cited by 1Web SearchBibTeXDownload
88Tunable and Energy Efficient Bus Encoding Techniques. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar. IEEE Trans. Computers (58): 1049-1062 (2009). Web SearchBibTeXDownload
87Reconfigurable Computing in the New Age of Parallelism. Walid A. Najjar, Jason R. Villarreal. SAMOS 2009, 255-262. Web SearchBibTeXDownload
2008
86Compiler generated systolic arrays for wavefront algorithm acceleration on FPGAs. Betul Buyukkurt, Walid A. Najjar. FPL 2008, 655-658. Web SearchBibTeXDownload
85Compiled hardware acceleration of Molecular Dynamics code. Jason R. Villarreal, Walid A. Najjar. FPL 2008, 667-670. Web SearchBibTeXDownload
84A Compiler Intermediate Representation for Reconfigurable Fabrics. Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar. International Journal of Parallel Programming (36): 493-520 (2008). Web SearchBibTeXDownload
83OpenFPGA CoreLib core library interoperability effort. Michael J. Wirthlin, Daniel S. Poznanovic, P. Sundararajan, Alan J. Coppola, D. Pellerin, Walid A. Najjar, R. Bruce, M. Babst, O. Pritchard, Paolo Palazzari, Georgi Kuzmanov. Parallel Computing (34): 231-244 (2008). Web SearchBibTeXDownload
82Efficient hardware code generation for FPGAs. Zhi Guo, Walid A. Najjar, Betul Buyukkurt. TACO (5) (2008). Web SearchBibTeXDownload
2007
81Compiling PCRE to FPGA for accelerating SNORT IDS. Abhishek Mitra, Walid A. Najjar, Laxmi N. Bhuyan. ANCS 2007, 127-136. Web SearchBibTeXDownload
80Compiling code accelerators for FPGAs. Walid A. Najjar. CASES 2007, 1-2. Web SearchBibTeXDownload
79Optimized Generation of Data-Path from C Codes for FPGAs. Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers. CoRR (abs/0710.4716) (2007). Web SearchBibTeXDownload
78A one-shot configurable-cache tuner for improved energy and performance. Ann Gordon-Ross, Pablo Viana, Frank Vahid, Walid A. Najjar, Edna Barros. DATE 2007, 755-760. Web SearchBibTeXDownload
77Dynamic Partial FPGA Reconfiguration in a Prototype Microprocessor System. Kai Schleupen, Scott Lekuch, Ryan Mannion, Zhi Guo, Walid A. Najjar, Frank Vahid. FPL 2007, 533-536. Web SearchBibTeXDownload
2006
76Compile-time area estimation for LUT-based FPGAs. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi. ACM Trans. Design Autom. Electr. Syst. (11): 104-122 (2006). Web SearchBibTeXDownload
75Impact of Loop Unrolling on Area, Throughput and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs. Betul Buyukkurt, Zhi Guo, Walid A. Najjar. ARC 2006, 401-412. Web SearchBibTeXDownload
74Automatic Compilation Framework for Bloom Filter Based Intrusion Detection. Dinesh C. Suresh, Zhi Guo, Betul Buyukkurt, Walid A. Najjar. ARC 2006, 413-418. Web SearchBibTeXDownload
73A Compiler Intermediate Representation for Reconfigurable Fabrics. Zhi Guo, Betul Buyukkurt, John Cortes, Abhishek Mitra, Walid A. Najjar. FPL 2006, 1-4. Web SearchBibTeXDownload
72Automation of IP Core Interface Generation for Reconfigurable Computing. Zhi Guo, Abhishek Mitra, Walid A. Najjar. FPL 2006, 1-6. Web SearchBibTeXDownload
71A code refinement methodology for performance-improved synthesis from C. Greg Stitt, Frank Vahid, Walid A. Najjar. ICCAD 2006, 716-723. Web SearchBibTeXDownload
70Dynamic Co-Processor Architecture for Software Acceleration on CSoCs. Abhishek Mitra, Zhi Guo, Anirban Banerjee, Walid A. Najjar. ICCD 2006. Web SearchBibTeXDownload
69Efficient indexing data structures for flash-based sensor devices. Song Lin, Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar. TOS (2): 468-503 (2006). Cited by 13Web SearchBibTeXDownload
2005
68A highly configurable cache for low energy embedded systems. Chuanjun Zhang, Frank Vahid, Walid A. Najjar. ACM Trans. Embedded Comput. Syst. (4): 363-387 (2005). Web SearchBibTeXDownload
67Optimized Generation of Data-Path from C Codes for FPGAs. Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers. DATE 2005, 112-117. Web SearchBibTeXDownload
66MicroHash: An Efficient Index Structure for Flash-Based Sensor Devices. Demetrios Zeinalipour-Yazti, Song Lin, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar. FAST 2005. Cited by 57Web SearchBibTeXDownload
65Techniques for synthesizing binaries to an advanced register/memory structure. Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid. FPGA 2005, 118-124. Web SearchBibTeXDownload
64VALVE: Variable Length Value Encoder for Off-Chip Data Buses.. Dinesh C. Suresh, Banit Agrawal, Walid A. Najjar, Jun Yang. ICCD 2005, 631-633. Web SearchBibTeXDownload
63Data Acquisition in Sensor Networks with Large Memories. Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Walid A. Najjar. ICDE Workshops 2005, 1188. Cited by 16Web SearchBibTeXDownload
62A tunable bus encoder for off-chip data buses. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar. ISLPED 2005, 319-322. Web SearchBibTeXDownload
61Towards In-Situ Data Storage in Sensor Databases. Demetrios Zeinalipour-Yazti, Vana Kalogeraki, Dimitrios Gunopulos, Anirban Mitra, Anirban Banerjee, Walid A. Najjar. Panhellenic Conference on Informatics 2005, 36-46. Cited by 7Web SearchBibTeXDownload
60Power Efficient Instruction Caches for Embedded Systems. Dinesh C. Suresh, Walid A. Najjar, Jun Yang. SAMOS 2005, 182-191. Web SearchBibTeXDownload
59Splitting the sensor node. Anirban Banerjee, Anirban Mitra, Walid A. Najjar. SenSys 2005, 270-271. Web SearchBibTeXDownload
58A way-halting cache for low-energy high-performance systems. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. TACO (2): 34-54 (2005). Cited by 37Web SearchBibTeXDownload
2004
57From Here to Main-stream: The Present and Future of Reconfigurable Computing. Walid A. Najjar. ERSA 2004, 17. Web SearchBibTeX
56A quantitative analysis of the speedup factors of FPGAs over processors. Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers. FPGA 2004, 162-170. Web SearchBibTeXDownload
55"How Long is Your Belt?" Towards a Single Device for Multiple Functions. Walid A. Najjar. ICPS 2004, 19-19. Web SearchBibTeXDownload
54A way-halting cache for low-energy high-performance systems. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. ISLPED 2004, 126-131. Cited by 37Web SearchBibTeXDownload
53Input data reuse in compiling window operations onto reconfigurable hardware. Zhi Guo, Betul Buyukkurt, Walid A. Najjar. LCTES 2004, 249-256. Web SearchBibTeXDownload
2003
52Automatic compilation to a coarse-grained reconfigurable system-opn-chip. Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm, Jeffrey Hammes. ACM Trans. Embedded Comput. Syst. (2): 560-589 (2003). Web SearchBibTeXDownload
51Power efficient encoding techniques for off-chip data buses. Dinesh C. Suresh, Banit Agrawal, Jun Yang, Walid A. Najjar, Laxmi N. Bhuyan. CASES 2003, 267-275. Web SearchBibTeXDownload
50First results with eBlocks: embedded systems building blocks. Susan Cotterell, Frank Vahid, Walid A. Najjar, Harry Hsieh. CODES+ISSS 2003, 168-175. Web SearchBibTeXDownload
49A Way-Halting Cache for Low-Energy High-Performance Systems. Chuanjun Zhang, Frank Vahid, Jun Yang, Walid A. Najjar. Computer Architecture Letters (2) (2003). Web SearchBibTeXDownload
48FV-MSB: A Scheme for Reducing Transition Activity on Data Buses. Dinesh C. Suresh, Jun Yang, Chuanjun Zhang, Banit Agrawal, Walid A. Najjar. HiPC 2003, 44-54. Web SearchBibTeXDownload
47High-Level Language Abstraction for Reconfigurable Computing. Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper, Jeffrey Hammes, Robert Rinker, J. Ross Beveridge, Monica Chawathe, Charles Ross. IEEE Computer (36): 63-69 (2003). Web SearchBibTeXDownload
46A Highly-Configurable Cache Architecture for Embedded Systems. Chuanjun Zhang, Frank Vahid, Walid A. Najjar. ISCA 2003, 136-146. Web SearchBibTeXDownload
45Energy Benefits of a Configurable Line Size Cache for Embedded Systems. Chuanjun Zhang, Frank Vahid, Walid A. Najjar. ISVLSI 2003, 87-91. Web SearchBibTeXDownload
44Profiling tools for hardware/software partitioning of embedded applications. Dinesh C. Suresh, Walid A. Najjar, Frank Vahid, Jason R. Villarreal, Greg Stitt. LCTES 2003, 189-198. Web SearchBibTeXDownload
2002
43Improving Software Performance with Configurable Logic. Jason R. Villarreal, Dinesh C. Suresh, Greg Stitt, Frank Vahid, Walid A. Najjar. Design Autom. for Emb. Sys. (7): 325-339 (2002). Web SearchBibTeXDownload
42Fast Area Estimation to Support Compiler Optimizations in FPGA-Based Reconfigurable Systems. Dhananjay Kulkarni, Walid A. Najjar, Robert Rinker, Fadi J. Kurdahi. FCCM 2002, 239. Web SearchBibTeXDownload
41Compiling ATR Probing Codes for Execution on FPGA Hardware. A. P. Wim Böhm, J. Ross Beveridge, Bruce A. Draper, Charlie Ross, Monica Chawathe, Walid A. Najjar. FCCM 2002, 301-302. Web SearchBibTeXDownload
40Mapping a Single Assignment Programming Language to Reconfigurable Systems. A. P. Wim Böhm, Jeffrey Hammes, Bruce A. Draper, Monica Chawathe, Charlie Ross, Robert Rinker, Walid A. Najjar. The Journal of Supercomputing (21): 117-130 (2002). Web SearchBibTeXDownload
2001
39A compiler framework for mapping applications to a coarse-grained reconfigurable computer architecture. Girish Venkataramani, Walid A. Najjar, Fadi J. Kurdahi, Nader Bagherzadeh, A. P. Wim Böhm. CASES 2001, 116-125. Web SearchBibTeXDownload
38The Sisal Project: Real World Functional Programming. Jean-Luc Gaudiot, Thomas DeBoni, John Feo, A. P. Wim Böhm, Walid A. Najjar, Patrick Miller. Compiler Optimizations for Scalable Parallel Systems Languages 2001, 45-72. Web SearchBibTeXDownload
37Compiling SA-C Programs to FPGAs: Performance Results. Bruce A. Draper, A. P. Wim Böhm, Jeffrey Hammes, Walid A. Najjar, J. Ross Beveridge, Charlie Ross, Monica Chawathe, Mitesh Desai, José Bins. ICVS 2001, 220-235. Web SearchBibTeXDownload
36A New Adaptive Hardware Tree-Based Multicast Routing in K-Ary N-Cubes. Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani. IEEE Trans. Computers (50): 647-659 (2001). Web SearchBibTeXDownload
35An automated process for compiling dataflow graphs into reconfigurable hardware. Robert Rinker, M. Carter, A. Patel, Monica Chawathe, Charlie Ross, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm. IEEE Trans. VLSI Syst. (9): 130-139 (2001). Web SearchBibTeXDownload
34Performance Evaluation of a New Hardware Supported Multicast Scheme for K-ary N-cubes. Dianne R. Kumar, Walid A. Najjar, Pradip K. Srimani. IPDPS 2001, 160. Web SearchBibTeX
33Loop fusion and temporal common subexpression elimination in window-based loops. Jeffrey Hammes, A. P. Wim Böhm, Charlie Ross, Monica Chawathe, Bruce A. Draper, Robert Rinker, Walid A. Najjar. IPDPS 2001, 142. Web SearchBibTeX
32Resource Management in Dataflow-Based Multithreaded Execution. Lucas Roh, Bhanu Shankar, A. P. Wim Böhm, Walid A. Najjar. J. Parallel Distrib. Comput. (61): 581-608 (2001). Web SearchBibTeXDownload
2000
31Compiling Image Processing Applications to Reconfigurable Hardware. Robert Rinker, Jeffrey Hammes, Walid A. Najjar, A. P. Wim Böhm, Bruce A. Draper. ASAP 2000, 56-65. Web SearchBibTeXDownload
30Compiling and Optimizing Image Processing Algorithms for FPGAs. Bruce A. Draper, Walid A. Najjar, A. P. Wim Böhm, Jeffrey Hammes, Robert Rinker, Charlie Ross, Monica Chawathe, José Bins. CAMP 2000, 222-231. Web SearchBibTeXDownload
29A High Level, Algorithmic Programming Language and Compiler for Reconfigurable Systems. Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper. PDPTA 2000. Web SearchBibTeX
1999
28Combining Adaptive and Deterministic Routing: Evaluation of a Hybrid Router. Dianne R. Kumar, Walid A. Najjar. CANPC 1999, 150-164. Web SearchBibTeXDownload
27Cameron: High level Language Compilation for Reconfigurable Systems. Jeffrey Hammes, Robert Rinker, A. P. Wim Böhm, Walid A. Najjar, Bruce A. Draper, J. Ross Beveridge. IEEE PACT 1999, 236-244. Web SearchBibTeXDownload
26Advances in the dataflow computational model. Walid A. Najjar, Edward A. Lee, Guang R. Gao. Parallel Computing (25): 1907-1929 (1999). Web SearchBibTeXDownload
1997
25Empirical Evaluation of Deterministic and Adaptive Routing with Constant-Area Routers. Dianne Miller, Walid A. Najjar. IEEE PACT 1997, 64. Web SearchBibTeXDownload
24Preliminary Evaluation of a Hybrid Deterministic/Adaptive Router. Dianne Miller, Walid A. Najjar. PCRCW 1997, 89-102. Web SearchBibTeXDownload
1996
23Generation, Optimization, and Evaluation of Multithreaded Code. Lucas Roh, Walid A. Najjar, Bhanu Shankar, A. P. Wim Böhm. J. Parallel Distrib. Comput. (32): 188-204 (1996). Web SearchBibTeXDownload
22Analysis of Buffer Design for Adaptive Routing in Direct Networks. Annette Lagman, Walid A. Najjar. MASCOTS 1996, 134-139. Web SearchBibTeX
1995
21Exploiting Data Structure Locality in the Dataflow Model. William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm. J. Parallel Distrib. Comput. (27): 183-200 (1995). Web SearchBibTeXDownload
20Design of storage hierarchy in multithreaded architectures. Lucas Roh, Walid A. Najjar. MICRO 1995, 271-278. Web SearchBibTeXDownload
1994
19Authors' Reply. Gühan Dündar, Vijay K. Bhargava. IEEE Trans. Computers (43): 1452-1453 (1994). Web SearchBibTeX
18An Analysis of Edge Fault Tolerance in Recursively Decomposable Regular Networks. Annette Lagman, Walid A. Najjar, Pradip K. Srimani. IEEE Trans. Computers (43): 470-475 (1994). Web SearchBibTeXDownload
17An Evaluation of Optimized Threaded Code Generation. Lucas Roh, Walid A. Najjar, Bhanu Shankar, A. P. Wim Böhm. IFIP PACT 1994, 37-46. Web SearchBibTeX
16A model for dataflow based vector execution. William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm. International Conference on Supercomputing 1994, 11-22. Web SearchBibTeXDownload
15Modeling Adaptive Routing in k-ary n-cube Networks. Walid A. Najjar, Annette Lagman, Sumit Sur, Pradip K. Srimani. MASCOTS 1994, 120-125. Web SearchBibTeX
1993
14The Initial Performance of a Bottom-Up Clustering Algorithm for Dataflow Graphs. Walid A. Najjar, Lucas Roh, A. P. Wim Böhm. Architectures and Compilation Techniques for Fine and Medium Grain Parallelism 1993, 91-100. Web SearchBibTeX
13Generation and Quantitative Evaluation of Dataflow Clusters. Lucas Roh, Walid A. Najjar, A. P. Wim Böhm. FPCA 1993, 159-168. Web SearchBibTeX
12A Quantitative Analysis of Dataflow Program Execution - Preliminaries to a Hybrid Design. Walid A. Najjar, A. P. Wim Böhm, William Marcus Miller. J. Parallel Distrib. Comput. (18): 314-326 (1993). Web SearchBibTeXDownload
11An evaluation of bottom-up and top-down thread generation techniques. A. P. Wim Böhm, Walid A. Najjar, Bhanu Shankar, Lucas Roh. MICRO 1993, 118-127. Web SearchBibTeXDownload
10Evaluation of Idealized Adaptive Routing on k-ary n-cubes. Annette Lagman, Walid A. Najjar, Sumit Sur, Pradip K. Srimani. SPDP 1993, 166-169. Web SearchBibTeX
1992
9An Analysis of Loop Latency in Dataflow Execution. Walid A. Najjar, William Marcus Miller, A. P. Wim Böhm. ISCA 1992, 352-360. Web SearchBibTeX
1991
8A Quantitative Analysis of Locality in Dataflow Programs. William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm. MICRO 1991, 12-18. Web SearchBibTeXDownload
1990
7A data-driven execution paradigm for distributed fault-tolerance. Walid A. Najjar, Jean-Luc Gaudiot. ACM SIGOPS European Workshop 1990. Web SearchBibTeXDownload
6Network Resilience: A Measure of Network Fault Tolerance. Walid A. Najjar, Jean-Luc Gaudiot. IEEE Trans. Computers (39): 174-181 (1990). Web SearchBibTeXDownload
1989
5A Single-Assignment Language in a Distributed Memory Multiprocessor. Paraskevas Evripidou, Walid A. Najjar, Jean-Luc Gaudiot. PARLE (2) 1989, 304-320. Web SearchBibTeXDownload
4Limits on Scalability in Gracefully Degradable Large-Scale Systems. Walid A. Najjar, Jean-Luc Gaudiot. SRDS 1989, 148-157. Web SearchBibTeX
1988
3Network Disconnection in Distributed Systems. Walid A. Najjar, Jean-Luc Gaudiot. ICDCS 1988, 554-561. Web SearchBibTeX
1987
2Reliability and Performance Modelling of Hypercube-Based Mutliprocessors. Walid A. Najjar, Jean-Luc Gaudiot. Computer Performance and Reliability 1987, 305-320. Web SearchBibTeX
1Multi-Level Execution In Data-Flow Architectures. Walid A. Najjar, Jean-Luc Gaudiot. ICPP 1987, 32-39. Web SearchBibTeX
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