| 2013 |
|---|
| 151 | Elastic Buffer Flow Control for On-Chip Networks. George Michelogiannakis, William J. Dally. IEEE Trans. Computers (62): 295-309 (2013). Web SearchBibTeXDownload |
| 150 | A 0.54pJ/b 20Gb/s ground-referenced single-ended short-haul serial link in 28nm CMOS for advanced packaging applications. John W. Poulton, William J. Dally, Xi Chen, John G. Eyles, Thomas H. Greer, Stephen G. Tell, C. Thomas Gray. ISSCC 2013, 404-405. Web SearchBibTeXDownload |
| 2012 |
|---|
| 149 | A Hierarchical Thread Scheduler and Register File for Energy-Efficient Throughput Processors. Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron. ACM Trans. Comput. Syst. (30): 8 (2012). Web SearchBibTeXDownload |
| 148 | Network congestion avoidance through Speculative Reservation. Nan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally. HPCA 2012, 443-454. Web SearchBibTeXDownload |
| 147 | Adaptive Backpressure: Efficient buffer management for on-chip networks. Daniel U. Becker, Nan Jiang, George Michelogiannakis, William J. Dally. ICCD 2012, 419-426. Web SearchBibTeXDownload |
| 146 | Unifying Primary Cache, Scratch, and Register File Memories in a Throughput Processor. Mark Gebhart, Stephen W. Keckler, Brucek Khailany, Ronny Krashinsky, William J. Dally. MICRO 2012, 96-106. Web SearchBibTeXDownload |
| 2011 |
|---|
| 145 | Packet Chaining: Efficient Single-Cycle Allocation for On-Chip Networks. George Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally. Computer Architecture Letters (10): 33-36 (2011). Web SearchBibTeXDownload |
| 144 | GPUs and the Future of Parallel Computing. Stephen W. Keckler, William J. Dally, Brucek Khailany, Michael Garland, David Glasco. IEEE Micro (31): 7-17 (2011). Web SearchBibTeXDownload |
| 143 | Evaluating Elastic Buffer and Wormhole Flow Control. George Michelogiannakis, Daniel U. Becker, William J. Dally. IEEE Trans. Computers (60): 896-903 (2011). Web SearchBibTeXDownload |
| 142 | Panel Statement. Per Stenström, William J. Dally, Jack Dongarra, Vipin Kumar, Robert Schreiber, Horst D. Simon, Uzi Vishkin. IPDPS 2011, 877. Web SearchBibTeXDownload |
| 141 | Energy-efficient mechanisms for managing thread context in throughput processors. Mark Gebhart, Daniel R. Johnson, David Tarjan, Stephen W. Keckler, William J. Dally, Erik Lindholm, Kevin Skadron. ISCA 2011, 235-246. Web SearchBibTeXDownload |
| 140 | Packet chaining: efficient single-cycle allocation for on-chip networks. George Michelogiannakis, Nan Jiang, Daniel U. Becker, William J. Dally. MICRO 2011, 83-94. Web SearchBibTeXDownload |
| 139 | A compile-time managed multi-level register file hierarchy. Mark Gebhart, Stephen W. Keckler, William J. Dally. MICRO 2011, 465-476. Web SearchBibTeXDownload |
| 2010 |
|---|
| 138 | The Even/Odd Synchronizer: A Fast, All-Digital, Periodic Synchronizer. William J. Dally, Stephen G. Tell. ASYNC 2010, 75-84. Web SearchBibTeXDownload |
| 137 | Fine-grain dynamic instruction placement for L0 scratch-pad memory. JongSoo Park, James D. Balfour, William J. Dally. CASES 2010, 137-146. Web SearchBibTeXDownload |
| 136 | Block-Parallel Programming for Real-Time Embedded Applications. David Black-Schaffer, William J. Dally. ICPP 2010, 297-306. Web SearchBibTeXDownload |
| 135 | Throughput computing. William J. Dally. ICS 2010, 2. Web SearchBibTeXDownload |
| 134 | The GPU Computing Era. John Nickolls, William J. Dally. IEEE Micro (30): 56-69 (2010). Web SearchBibTeXDownload |
| 133 | Moving the needle, computer architecture research in academe and industry. William J. Dally. ISCA 2010, 1. Web SearchBibTeXDownload |
| 132 | Evaluating Bufferless Flow Control for On-chip Networks. George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis. NOCS 2010, 9-16. Web SearchBibTeXDownload |
| 131 | Buffer-space efficient and deadlock-free scheduling of stream applications on multi-core architectures. JongSoo Park, William J. Dally. SPAA 2010, 1-10. Web SearchBibTeXDownload |
| 2009 |
|---|
| 130 | Operand Registers and Explicit Operand Forwarding. James D. Balfour, R. C. Halting, William J. Dally. Computer Architecture Letters (8): 60-63 (2009). Web SearchBibTeXDownload |
| 129 | Elastic-buffer flow control for on-chip networks. George Michelogiannakis, James D. Balfour, William J. Dally. HPCA 2009, 151-162. Web SearchBibTeXDownload |
| 128 | Cost-Efficient Dragonfly Topology for Large-Scale Systems. John Kim, William J. Dally, Steve Scott, Dennis Abts. IEEE Micro (29): 33-40 (2009). Web SearchBibTeXDownload |
| 127 | Indirect adaptive routing on large scale interconnection networks. Nan Jiang, John Kim, William J. Dally. ISCA 2009, 220-231. Web SearchBibTeXDownload |
| 126 | Allocator implementations for network-on-chip routers. Daniel U. Becker, William J. Dally. SC 2009. Web SearchBibTeXDownload |
| 125 | Router designs for elastic buffer on-chip networks. George Michelogiannakis, William J. Dally. SC 2009. Web SearchBibTeXDownload |
| 2008 |
|---|
| 124 | Hierarchical Instruction Register Organization. David Black-Schaffer, James D. Balfour, William J. Dally, Vishal Parikh, JongSoo Park. Computer Architecture Letters (7): 41-44 (2008). Web SearchBibTeXDownload |
| 123 | Stream Scheduling: A Framework to Manage Bulk Operations in Memory Hierarchies. Abhishek Das, William J. Dally. Euro-Par 2008, 337-349. Web SearchBibTeXDownload |
| 122 | Efficient Embedded Computing. William J. Dally, James D. Balfour, David Black-Schaffer, James Chen, R. Curtis Harting, Vishal Parikh, JongSoo Park, David Sheffield. IEEE Computer (41): 27-32 (2008). Web SearchBibTeXDownload |
| 121 | Technology-Driven, Highly-Scalable Dragonfly Topology. John Kim, William J. Dally, Steve Scott, Dennis Abts. ISCA 2008, 77-88. Web SearchBibTeXDownload |
| 120 | A tuning framework for software-managed memory hierarchies. Manman Ren, Ji Young Park, Mike Houston, Alex Aiken, William J. Dally. PACT 2008, 280-291. Web SearchBibTeXDownload |
| 119 | A portable runtime interface for multi-level memory hierarchies. Mike Houston, Ji Young Park, Manman Ren, Timothy J. Knight, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan. PPOPP 2008, 143-152. Web SearchBibTeXDownload |
| 2007 |
|---|
| 118 | An Energy-Efficient Processor Architecture for Embedded Systems. James D. Balfour, William J. Dally, David Black-Schaffer, Vishal Parikh, JongSoo Park. Computer Architecture Letters (7): 29-32 (2007). Web SearchBibTeXDownload |
| 117 | Register pointer architecture for efficient embedded processors. JongSoo Park, Sung-Boem Park, James D. Balfour, David Black-Schaffer, Christos Kozyrakis, William J. Dally. DATE 2007, 600-605. Web SearchBibTeXDownload |
| 116 | Interconnect-Centric Computing. William J. Dally. HPCA 2007, 1. Web SearchBibTeXDownload |
| 115 | Tradeoff between data-, instruction-, and thread-level parallelism in stream processors. Jung Ho Ahn, Mattan Erez, William J. Dally. ICS 2007, 126-137. Web SearchBibTeXDownload |
| 114 | Executing irregular scientific applications on stream architectures. Mattan Erez, Jung Ho Ahn, Jayanth Gummaraju, Mendel Rosenblum, William J. Dally. ICS 2007, 93-104. Web SearchBibTeXDownload |
| 113 | Research Challenges for On-Chip Interconnection Networks. John D. Owens, William J. Dally, Ron Ho, D. N. Jayasimha, Stephen W. Keckler, Li-Shiuan Peh. IEEE Micro (27): 96-108 (2007). Web SearchBibTeXDownload |
| 112 | Flattened butterfly: a cost-efficient topology for high-radix networks. John Kim, William J. Dally, Dennis Abts. ISCA 2007, 126-137. Web SearchBibTeXDownload |
| 111 | Future of on-chip interconnection architectures. Shekhar Borkar, William J. Dally. ISLPED 2007, 122. Web SearchBibTeXDownload |
| 110 | Flattened Butterfly Topology for On-Chip Networks. John Kim, James D. Balfour, William J. Dally. MICRO 2007, 172-182. Web SearchBibTeXDownload |
| 109 | Enabling Technology for On-Chip Interconnection Networks. William J. Dally. NOCS 2007, 3. Web SearchBibTeXDownload |
| 108 | Stream Scheduling: A Framework to Manage Bulk Operations in a Memory Hierarchy. Abhishek Das, William J. Dally. PACT 2007, 405. Web SearchBibTeXDownload |
| 107 | Architectural Support for the Stream Execution Model on General-Purpose Processors. Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally. PACT 2007, 3-12. Web SearchBibTeXDownload |
| 106 | Compilation for explicitly managed memory hierarchies. Timothy J. Knight, Ji Young Park, Manman Ren, Mike Houston, Mattan Erez, Kayvon Fatahalian, Alex Aiken, William J. Dally, Pat Hanrahan. PPOPP 2007, 226-236. Web SearchBibTeXDownload |
| 2006 |
|---|
| 105 | Topology optimization of interconnection networks. Amit K. Gupta, William J. Dally. Computer Architecture Letters (5): 10-13 (2006). Web SearchBibTeXDownload |
| 104 | Data parallel address architecture. Jung Ho Ahn, William J. Dally. Computer Architecture Letters (5): 30-33 (2006). Web SearchBibTeXDownload |
| 103 | Computer Architecture in the Many-Core Era. William J. Dally. ICCD 2006. Web SearchBibTeXDownload |
| 102 | Design tradeoffs for tiled CMP on-chip networks. James D. Balfour, William J. Dally. ICS 2006, 187-198. Web SearchBibTeXDownload |
| 101 | The BlackWidow High-Radix Clos Network. Steve Scott, Dennis Abts, John Kim, William J. Dally. ISCA 2006, 16-28. Web SearchBibTeXDownload |
| 100 | Compiling for stream processing. Abhishek Das, William J. Dally, Peter R. Mattson. PACT 2006, 33-42. Web SearchBibTeXDownload |
| 99 | Interconnect routing and scheduling - Adaptive routing in high-radix clos network. John Kim, William J. Dally, Dennis Abts. SC 2006, 92. Web SearchBibTeXDownload |
| 98 | Multi-core issues - Multi-Core for HPC: breakthrough or breakdown?. Thomas L. Sterling, Peter M. Kogge, William J. Dally, Steve Scott, William Gropp, David E. Keyes, Peter H. Beckman. SC 2006, 73. Web SearchBibTeXDownload |
| 97 | Memory - Sequoia: programming the memory hierarchy. Kayvon Fatahalian, Daniel Reiter Horn, Timothy J. Knight, Larkhoon Leem, Mike Houston, Ji Young Park, Mattan Erez, Manman Ren, Alex Aiken, William J. Dally, Pat Hanrahan. SC 2006, 83. Web SearchBibTeXDownload |
| 96 | Architecture - The design space of data-parallel memory systems. Jung Ho Ahn, Mattan Erez, William J. Dally. SC 2006, 80. Web SearchBibTeXDownload |
| 2005 |
|---|
| 95 | Explaining the gap between ASIC and custom power: a custom perspective. Andrew Chang, William J. Dally. DAC 2005, 281-284. Web SearchBibTeXDownload |
| 94 | Scatter-Add in Data Parallel Architectures. Jung Ho Ahn, Mattan Erez, William J. Dally. HPCA 2005, 132-142. Web SearchBibTeXDownload |
| 93 | Hot Chips 16: Power, Parallelism, and Memory Performance. William J. Dally, Keith Diefendorff. IEEE Micro (25): 8-9 (2005). Web SearchBibTeXDownload |
| 92 | Microarchitecture of a High-Radix Router. John Kim, William J. Dally, Brian Towles, Amit K. Gupta. ISCA 2005, 420-431. Web SearchBibTeXDownload |
| 91 | Fault Tolerance Techniques for the Merrimac Streaming Supercomputer. Mattan Erez, Nuwan Jayasena, Timothy J. Knight, William J. Dally. SC 2005, 29. Web SearchBibTeXDownload |
| 2004 |
|---|
| 90 | Stream Processors: Progammability and Efficiency. William J. Dally, Ujval J. Kapasi, Brucek Khailany, Jung Ho Ahn, Abhishek Das. ACM Queue (2): 52-62 (2004). Web SearchBibTeXDownload |
| 89 | Buffer and Delay Bounds in High Radix Interconnection Networks. Arjun Singh, William J. Dally. Computer Architecture Letters (3) (2004). Web SearchBibTeXDownload |
| 88 | Globally Adaptive Load-Balanced Routing on Tori. Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta. Computer Architecture Letters (3) (2004). Web SearchBibTeXDownload |
| 87 | Stream Register Files with Indexed Access. Nuwan Jayasena, Mattan Erez, Jung Ho Ahn, William J. Dally. HPCA 2004, 60-72. Web SearchBibTeXDownload |
| 86 | Evaluating the Imagine Stream Architecture. Jung Ho Ahn, William J. Dally, Brucek Khailany, Ujval J. Kapasi, Abhishek Das. ISCA 2004, 14-25. Web SearchBibTeXDownload |
| 85 | Analysis and Performance Results of a Molecular Modeling Application on Merrimac. Mattan Erez, Jung Ho Ahn, Ankit Garg, William J. Dally, Eric Darve. SC 2004, 42. Web SearchBibTeXDownload |
| 84 | Adaptive channel queue routing on k-ary n-cubes. Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles. SPAA 2004, 11-19. Web SearchBibTeXDownload |
| 2003 |
|---|
| 83 | Exploring the VLSI Scalability of Stream Processors. Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles. HPCA 2003, 153-164. Web SearchBibTeXDownload |
| 82 | CMOS High-Speed I/Os - Present and Future. M.-J. Edward Lee, William J. Dally, Ramin Farjad-Rad, Hiok-Tiaq Ng, Ramesh Senthinathan, John H. Edmondson, John Poulton. ICCD 2003, 454-461. Web SearchBibTeXDownload |
| 81 | Guaranteed scheduling for switches with configuration overhead. Brian Towles, William J. Dally. IEEE/ACM Trans. Netw. (11): 835-847 (2003). Web SearchBibTeXDownload |
| 80 | Programmable Stream Processors. Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahn, Peter R. Mattson, John D. Owens. IEEE Computer (36): 54-62 (2003). Web SearchBibTeXDownload |
| 79 | GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks. Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles. ISCA 2003, 194-205. Web SearchBibTeXDownload |
| 78 | Merrimac: Supercomputing with Streams. William J. Dally, Francois Labonte, Abhishek Das, Pat Hanrahan, Jung Ho Ahn, Jayanth Gummaraju, Mattan Erez, Nuwan Jayasena, Ian Buck, Timothy J. Knight, Ujval J. Kapasi. SC 2003, 35. Web SearchBibTeXDownload |
| 77 | Throughput-centric routing algorithm design. Brian Towles, William J. Dally, Stephen P. Boyd. SPAA 2003, 200-209. Web SearchBibTeXDownload |
| 2002 |
|---|
| 76 | Migration in Single Chip Multiprocessors. K. A. Shaw, William J. Dally. Computer Architecture Letters (1) (2002). Web SearchBibTeXDownload |
| 75 | Worst-case Traffic for Oblivious Routing Functions. Brian Towles, William J. Dally. Computer Architecture Letters (1) (2002). Web SearchBibTeXDownload |
| 74 | Scalable Opto-Electronic Network (SOENet). Amit K. Gupta, William J. Dally, Arjun Singh, Brian Towles. Hot Interconnects 2002, 71-76. Web SearchBibTeXDownload |
| 73 | A Stream Processor Development Platform. Ben Serebrin, John D. Owens, Chen H. Chen, Stephen P. Crago, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, Scott Rixner, William J. Dally. ICCD 2002, 303. Web SearchBibTeXDownload |
| 72 | The Imagine Stream Processor. Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany. ICCD 2002, 282-288. Web SearchBibTeXDownload |
| 71 | Media Processing Applications on the Imagine Stream Processor. John D. Owens, Scott Rixner, Ujval J. Kapasi, Peter R. Mattson, Brian Towles, Ben Serebrin, William J. Dally. ICCD 2002, 295-302. Web SearchBibTeXDownload |
| 70 | VLSI Design and Verification of the Imagine Processor. Brucek Khailany, William J. Dally, Andrew Chang, Ujval J. Kapasi, Jinyung Namkoong, Brian Towles. ICCD 2002, 289-294. Web SearchBibTeXDownload |
| 69 | Guaranteed Scheduling for Switches with Configuration Overhead. Brian Towles, William J. Dally. INFOCOM 2002. Web SearchBibTeXDownload |
| 68 | Locality-preserving randomized oblivious routing on torus networks. Arjun Singh, William J. Dally, Brian Towles, Amit K. Gupta. SPAA 2002, 9-13. Web SearchBibTeXDownload |
| 67 | Worst-case traffic for oblivious routing functions. Brian Towles, William J. Dally. SPAA 2002, 1-8. Web SearchBibTeXDownload |
| 2001 |
|---|
| 66 | Route Packets, Not Wires: On-Chip Interconnection Networks. William J. Dally, Brian Towles. DAC 2001, 684-689. Web SearchBibTeXDownload |
| 65 | A Delay Model and Speculative Architecture for Pipelined Routers. Li-Shiuan Peh, William J. Dally. HPCA 2001, 255-266. Web SearchBibTeXDownload |
| 64 | Guest Editors' Introduction: Hot Chips 12. William J. Dally, Marc Tremblay, Allen J. Baum. IEEE Micro (21): 13-15 (2001). Web SearchBibTeXDownload |
| 63 | Imagine: Media Processing with Streams. Brucek Khailany, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, Jinyung Namkoong, John D. Owens, Brian Towles, Andrew Chang, Scott Rixner. IEEE Micro (21): 35-46 (2001). Web SearchBibTeXDownload |
| 62 | A Delay Model for Router Microarchitectures. Li-Shiuan Peh, William J. Dally. IEEE Micro (21): 26-34 (2001). Web SearchBibTeXDownload |
| 61 | Monolithic chaotic communications system. P. Chiang, William J. Dally, E. Lee. ISCAS (3) 2001, 325-328. Web SearchBibTeXDownload |
| 2000 |
|---|
| 60 | Communication Scheduling. Peter R. Mattson, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens. ASPLOS 2000, 82-92. Web SearchBibTeXDownload |
| 59 | The role of custom design in ASIC Chips. William J. Dally, Andrew Chang. DAC 2000, 643-647. Web SearchBibTeXDownload |
| 58 | Register Organization for Media Processing. Scott Rixner, William J. Dally, Brucek Khailany, Peter R. Mattson, Ujval J. Kapasi, John D. Owens. HPCA 2000, 375-386. Web SearchBibTeXDownload |
| 57 | Flit-Reservation Flow Control. Li-Shiuan Peh, William J. Dally. HPCA 2000, 73-84. Web SearchBibTeXDownload |
| 56 | Smart Memories: a modular reconfigurable architecture. Ken Mai, Tim Paaske, Nuwan Jayasena, Ron Ho, William J. Dally, Mark Horowitz. ISCA 2000, 161-171. Web SearchBibTeXDownload |
| 55 | Memory access scheduling. Scott Rixner, William J. Dally, Ujval J. Kapasi, Peter R. Mattson, John D. Owens. ISCA 2000, 128-138. Web SearchBibTeXDownload |
| 54 | Processor Mechanisms for Software Shared Memory. Nicholas P. Carter, William J. Dally, Whay Sing Lee, Stephen W. Keckler, Andrew Chang. ISHPC 2000, 120-133. Web SearchBibTeXDownload |
| 53 | Efficient conditional operations for data-parallel architectures. Ujval J. Kapasi, William J. Dally, Scott Rixner, Peter R. Mattson, John D. Owens, Brucek Khailany. MICRO 2000, 159-170. Web SearchBibTeXDownload |
| 1999 |
|---|
| 52 | VLSI Architecture: Past, Present, and Future. William J. Dally, Steve Lacy. ARVLSI 1999, 232-241. Web SearchBibTeXDownload |
| 51 | Concurrent Event Handling through Multithreading. Stephen W. Keckler, Andrew Chang, Whay Sing Lee, Sandeep Chatterjee, William J. Dally. IEEE Trans. Computers (48): 903-916 (1999). Web SearchBibTeXDownload |
| 1998 |
|---|
| 50 | Architecture of a Message-Driven Processor. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills. 25 Years ISCA: Retrospectives and Reprints 1998, 337-344. Web SearchBibTeXDownload |
| 49 | Retrospective: the J-machine. William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, Ellen Spertus, Deborah A. Wallach, D. Scott Wills, Andrew Chang, John S. Keen. 25 Years ISCA: Retrospectives and Reprints 1998, 54-58. Web SearchBibTeXDownload |
| 48 | The effects of explicitly parallel mechanisms on the multi-ALU processor cluster pipeline. Andrew Chang, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Whay Sing Lee. ICCD 1998, 474-481. Web SearchBibTeXDownload |
| 47 | An Efficient, Protected Message Interface. Whay Sing Lee, William J. Dally, Stephen W. Keckler, Nicholas P. Carter, Andrew Chang. IEEE Computer (31): 69-75 (1998). Web SearchBibTeXDownload |
| 46 | Exploiting Fine-grain Thread Level Parallelism on the MIT Multi-ALU Processor. Stephen W. Keckler, William J. Dally, Daniel Maskit, Nicholas P. Carter, Andrew Chang, Whay Sing Lee. ISCA 1998, 306-317. Web SearchBibTeXDownload |
| 45 | A Bandwidth-efficient Architecture for Media Processing. Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens. MICRO 1998, 3-13. Web SearchBibTeXDownload |
| 44 | Point Sample Rendering. J. P. Grossman, William J. Dally. Rendering Techniques 1998, 181-192. Web SearchBibTeX |
| 1997 |
|---|
| 43 | Extended Ehemeral Logging: Log Storage Management for Applications with Long Lived Transactions. John S. Keen, William J. Dally. ACM Trans. Database Syst. (22): 1-42 (1997). Web SearchBibTeXDownload |
| 42 | The M-machine multicomputer. Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee. International Journal of Parallel Programming (25): 183-212 (1997). Web SearchBibTeXDownload |
| 1995 |
|---|
| 41 | Low-latency plesiochronous data retiming. Larry R. Dennison, William J. Dally, Thucydides Xanthopoulos. ARVLSI 1995, 304-315. Web SearchBibTeXDownload |
| 40 | Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors. Stuart Fiske, William J. Dally. HPCA 1995, 210-221. Web SearchBibTeXDownload |
| 39 | The Named-State Register File: Implementation and Performance. Peter R. Nuth, William J. Dally. HPCA 1995, 4-13. Web SearchBibTeXDownload |
| 38 | The M-Machine multicomputer. Marco Fillo, Stephen W. Keckler, William J. Dally, Nicholas P. Carter, Andrew Chang, Yevgeny Gurevich, Whay Sing Lee. MICRO 1995, 146-156. Web SearchBibTeXDownload |
| 37 | Evaluating the Locality Benefits of Active Messages. Ellen Spertus, William J. Dally. PPOPP 1995, 189-198. Web SearchBibTeXDownload |
| 1994 |
|---|
| 36 | Hardware Support for Fast Capability-based Addressing. Nicholas P. Carter, Stephen W. Keckler, William J. Dally. ASPLOS 1994, 319-327. Web SearchBibTeXDownload |
| 35 | XEL: Extended Ephemeral Logging for Log Storage Management. John S. Keen, William J. Dally. CIKM 1994, 312-321. Web SearchBibTeXDownload |
| 34 | The Reliable Router: A Reliable and High-Performance Communication Substrate for Parallel Computers. William J. Dally, Larry R. Dennison, David Harris, Kinhong Kan, Thucydides Xanthopoulos. PCRCW 1994, 241-255. Web SearchBibTeXDownload |
| 1993 |
|---|
| 33 | Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels. William J. Dally, Hiromichi Aoki. IEEE Trans. Parallel Distrib. Syst. (4): 466-475 (1993). Web SearchBibTeXDownload |
| 32 | The J-Machine Multicomputer: An Architectural Evaluation. Michael D. Noakes, Deborah A. Wallach, William J. Dally. ISCA 1993, 224-235. Web SearchBibTeXDownload |
| 31 | Evaluation of Mechanisms for Fine-Grained Parallel Programs in the J-Machine and the CM-5. Ellen Spertus, Seth Copen Goldstein, Klaus E. Schauser, Thorsten von Eicken, David E. Culler, William J. Dally. ISCA 1993, 302-313. Web SearchBibTeXDownload |
| 30 | A Universal Parallel Computer Architecture. William J. Dally. New Generation Comput. (11): 227-249 (1993). Web SearchBibTeXDownload |
| 29 | Performance Evaluation of Ephemeral Logging. John S. Keen, William J. Dally. SIGMOD Conference 1993, 187-196. Web SearchBibTeXDownload |
| 1992 |
|---|
| 28 | A Universal Parallel Computer Architecture. William J. Dally. FGCS 1992, 746-758. Web SearchBibTeX |
| 27 | The J-Machine Network. Peter R. Nuth, William J. Dally. ICCD 1992, 420-423. Web SearchBibTeX |
| 26 | The Message Driven Processor: An Integrated Multicomputer Processing Element. William J. Dally, Andrew A. Chien, Stuart Fiske, Greg Fyler, Waldemar Horwat, John S. Keen, Richard A. Lethin, Michael D. Noakes, Peter R. Nuth, D. Scott Wills. ICCD 1992, 416-419. Web SearchBibTeX |
| 25 | MDP Design Tools and Methods. Richard A. Lethin, William J. Dally. ICCD 1992, 424-428. Web SearchBibTeX |
| 24 | A Fast Translation Method for Paging on top of Segmentation. William J. Dally. IEEE Trans. Computers (41): 247-250 (1992). Web SearchBibTeXDownload |
| 23 | Virtual-Channel Flow Control. William J. Dally. IEEE Trans. Parallel Distrib. Syst. (3): 194-205 (1992). Web SearchBibTeXDownload |
| 22 | Processor Coupling: Integrating Compile Time and Runtime Scheduling for Parallelism. Stephen W. Keckler, William J. Dally. ISCA 1992, 202-213. Web SearchBibTeXDownload |
| 1991 |
|---|
| 21 | A Mechanism for Efficient Context Switching. Peter R. Nuth, William J. Dally. ICCD 1991, 301-304. Web SearchBibTeX |
| 20 | Experiences Implementing Dataflow on a General-Purpose Parallel Computer. Ellen Spertus, William J. Dally. ICPP (2) 1991, 231-235. Web SearchBibTeX |
| 19 | Express Cubes: Improving the Performance of k-Ary n-Cube Interconnection Networks. William J. Dally. IEEE Trans. Computers (40): 1016-1023 (1991). Web SearchBibTeXDownload |
| 1990 |
|---|
| 18 | Performance Analysis of k-Ary n-Cube Interconnection Networks. William J. Dally. IEEE Trans. Computers (39): 775-785 (1990). Web SearchBibTeXDownload |
| 17 | A hardware logic simulation system. Prathima Agrawal, William J. Dally. IEEE Trans. on CAD of Integrated Circuits and Systems (9): 19-29 (1990). Web SearchBibTeXDownload |
| 16 | Virtual-Channel Flow Control. William J. Dally. ISCA 1990, 60-68. Web SearchBibTeXDownload |
| 15 | Concurrent Aggregates (CA). Andrew A. Chien, William J. Dally. PPOPP 1990, 187-196. Web SearchBibTeXDownload |
| 1989 |
|---|
| 14 | Micro-Optimization of Floating Point Operations. William J. Dally. ASPLOS 1989, 283-289. Web SearchBibTeXDownload |
| 13 | Algorithms for Accuracy Enhancement in a Hardware Logic Simulator. Prathima Agrawal, R. Tutundjian, William J. Dally. DAC 1989, 645-648. Web SearchBibTeXDownload |
| 12 | The J-Machine: A Fine-Gain Concurrent Computer. William J. Dally, Andrew A. Chien, Stuart Fiske, Waldemar Horwat, John S. Keen, Michael Larivee, Richard A. Lethin, Peter R. Nuth, D. Scott Wills. IFIP Congress 1989, 1147-1153. Web SearchBibTeX |
| 11 | Universal Mechanisms for Concurrency. William J. Dally, D. Scott Wills. PARLE (1) 1989, 19-33. Web SearchBibTeXDownload |
| 10 | Experience with CST: Programming and Implementation. Waldemar Horwat, Andrew A. Chien, William J. Dally. PLDI 1989, 101-109. Web SearchBibTeXDownload |
| 9 | Object-oriented concurrent programming in CST. William J. Dally, Andrew A. Chien. SIGPLAN Notices (24): 28-31 (1989). Web SearchBibTeXDownload |
| 1988 |
|---|
| 8 | Mechanisms for Concurrent Computing. William J. Dally. FGCS 1988, 154-156. Web SearchBibTeX |
| 7 | The Reconfigurable Arithmetic Processor. Stuart Fiske, William J. Dally. ISCA 1988, 30-36. Web SearchBibTeXDownload |
| 1987 |
|---|
| 6 | Architecture and Design of the MARS Hardware Accelerator. Prathima Agrawal, William J. Dally, Ahmed K. Ezzat, W. C. Fischer, H. V. Jagadish, A. S. Krishnakumar. DAC 1987, 101-107. Cited by 17Web SearchBibTeXDownload |
| 5 | Deadlock-Free Message Routing in Multiprocessor Interconnection Networks. William J. Dally, Charles L. Seitz. IEEE Trans. Computers (36): 547-553 (1987). Web SearchBibTeXDownload |
| 4 | Architecture of a Message-Driven Processor. William J. Dally, Linda Chao, Andrew A. Chien, Soha Hassoun, Waldemar Horwat, Jon Kaplan, Paul Song, Brian Totty, D. Scott Wills. ISCA 1987, 189-196. Web SearchBibTeXDownload |
| 1986 |
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| 3 | The Torus Routing Chip. William J. Dally, Charles L. Seitz. Distributed Computing (1): 187-196 (1986). Web SearchBibTeXDownload |
| 1985 |
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| 2 | A Hardware Architecture for Switch-Level Simulation. William J. Dally, Randal E. Bryant. IEEE Trans. on CAD of Integrated Circuits and Systems (4): 239-250 (1985). Web SearchBibTeXDownload |
| 1 | An Object Oriented Architecture. William J. Dally, James T. Kajiya. ISCA 1985, 154-161. Web SearchBibTeXDownload |
