Yatin Vasant Hoskote
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- Sorted by Year/Conf, Year/Citation, Citation
| 1997 | ||
|---|---|---|
| 4 | Automatic verification of implementations of large circuits against HDL specifications. Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell, John Moondanos. IEEE Trans. on CAD of Integrated Circuits and Systems (16): 217-228 (1997). Web SearchBibTeXDownload | |
| 1996 | ||
| 3 | Verification of All Circuits in a Floating-Point Unit Using Word-Level Model Checking. Yirng-An Chen, Edmund M. Clarke, Pei-Hsin Ho, Yatin Vasant Hoskote, Timothy Kam, Manpreet Khaira, John W. O'Leary, Xudong Zhao. FMCAD 1996, 19-33. Cited by 55Web SearchBibTeXDownload | |
| 1995 | ||
| 2 | Automated verification of temporal properties specified as state machines in VHDL. Yatin Vasant Hoskote, Jacob A. Abraham, Donald S. Fussell. Great Lakes Symposium on VLSI 1995, 100-105. Web SearchBibTeXDownload | |
| 1994 | ||
| 1 | Verification of Circuits Described in VHDL through Extraction of Design Intent. Yatin Vasant Hoskote, John Moondanos, Jacob A. Abraham, Donald S. Fussell. VLSI Design 1994, 417-420. Web SearchBibTeX | |
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